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* superiotool/ite: add IT8625E EC registersMichał Kopeć2022-04-061-0/+37
| | | | | | | | | | | | | | Add support for dumping ITE IT8625E Environmental Controller registers. Values as per "IT8625E Preliminary Specification V0.3 (For D Version)". Change-Id: I68aad90097206c6b8ef40075530c00809d9511e2 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* amdfwtool: Add a macro to set explicitly second gen for old SOCsZheng Bao2022-04-052-1/+6
| | | | | | | | | | | | It is more reasonable than getting the value from memset. For the reserved bits, keep them as they were for old SOCs. Change-Id: I65caa11e835d2ff52bec4b8904057bbced434891 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* util/spd_tools: Add ability to override SPD file for partsRobert Zieba2022-04-052-27/+64
| | | | | | | | | | | | | | | This commit adds the ability to override the SPD file that is used for a specific part. BUG=b:224884904 TEST=Verified that generated makefile uses specified SPD file and that it remains unchanged when this capability is not used Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I078dd04fead2bf19f53bc6ca8295187d439adc20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* crossgcc: Upgrade IASL from 20211217 to 20220331Elyes Haouas2022-04-044-2/+2
| | | | | | | | | | | | | "REDUNDANT_OFFSET_REMARK" to ignore redundant offset remarks is not needed any more as it’s included upstream. Changes: https://acpica.org/node/199 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ice7f9a10051f7f62c53098161fd2f498d724c17d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* crossgcc: Upgrade CMake from 3.22.2 to 3.23.0Elyes Haouas2022-04-043-2/+2
| | | | | | | | | | | Release Notes: https://cmake.org/cmake/help/v3.23/release/3.23.html Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ib31124baa3cae65211ad361a7d41c9504105be91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* util/amdfwtool/data_parse: fix SPL table handling regressionFelix Held2022-04-031-2/+2
| | | | | | | | | | | | | Use the SPL table binary from the config file if no override is specified via the spl-table command line argument. This fixes a regression caused by commit 6c5ec8e31ccbe3d9bbf201c956fc3b54703a9767 (amdfwtool: Add options to support mainboard specific SPL table). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I93419a878b41b1dfcbf58d930740aaae553120f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/cbmem: add type castPaul Fagerburg2022-04-021-1/+1
| | | | | | | | | | | | | | arch_convert_raw_ts_entry returns a uint64_t, which needs to be cast on ARM systems to avoid a type error. BUG=b/227871959 TEST=no build errors in downstream Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: I87a83758b7f122b77f9631c669c7cd8df66f8d1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63317 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/ifittool: Fix clearing FIT when setting the pointerArthur Heymans2022-04-011-7/+15
| | | | | | | | | | | | | When setting the FIT pointer, the FIT table is only known later in the codeflow. Change-Id: I658f4fffa997d1f7beaf6d6ae37d2885ae602e5c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63035 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/cbmem: Add FlameGraph-compatible timestamps outputJakub Czapiga2022-03-311-21/+117
| | | | | | | | | | | | | | | | | | | | Flame graphs are used to visualize hierarchical data, like call stacks. Timestamps collected by coreboot can be processed to resemble profiler-like output, and thus can be feed to flame graph generation tools. Generating flame graph using https://github.com/brendangregg/FlameGraph: cbmem -S > trace.txt FlameGraph/flamegraph.pl --flamechart trace.txt > output.svg TEST=Run on coreboot-enabled device and extract timestamps using -t/-T/-S options Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I3a4e20a267e9e0fbc6b3a4d6a2409b32ce8fca33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* util/amdfwtool: use ISH support for Sabrina SoCFelix Held2022-03-301-0/+11
| | | | | | | | | | | The PSP in the Sabrina SoC uses the image slot header to find the second level PSP directory table, so it needs the ISH to be generated. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9e6308854147c9f6f72d722215c833ee86ee4f94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63186 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool: add Sabrina SoC typeFelix Held2022-03-301-0/+6
| | | | | | | | | | | | Add PLATFORM_SABRINA to the enum of supported platforms and integrate it into the existing code. Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibe52b44395619f697686bd900a522562abbe7646 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/amdfwtool: select A/B recovery when ISH is usedFelix Held2022-03-301-4/+6
| | | | | | | | | | | | | In newer AMD SoCs, the image slot header is used in the AMD A/B recovery scheme, so set recovery_ab to true when need_ish is true. Also move the block of code before the process_config call, since that call will already use the recovery_ab field of the cb_config struct. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I65903765514f215bf5cc9b949d0b95aff781eb34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63184 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool: use table-relative addressing in ISH caseFelix Held2022-03-301-1/+3
| | | | | | | | | | | When the image slot header (ISH) is used, the addresses in the PSP and BIOS directory tables need to be relative to the beginning of the table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia61f7c8313d5a1af95c68b9177a53a2f5443552a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/genbuild_h: micro-adjust the regexp used to set COREBOOT_MAJOR_VERSIONIdwer Vollering2022-03-301-1/+1
| | | | | | | | | | | | | | | | On FreeBSD, every build target would show warnings from its builtin printf(). Change the regexp to be compatible with BSD sed. This will avoid noise like "printf: 4.14-1278-g5d74ccf1c3: not completely converted". Signed-off-by: Idwer Vollering <vidwer@gmail.com> Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Change-Id: I1c0c260fd8d42e23a612a353a288e472cc068c8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
* amdfwtool: Clear the whole byte of EFS_GENZheng Bao2022-03-291-0/+1
| | | | | | | | Change-Id: I434e031e906f73362b1e920e034fa15a8d078ab2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Add ISH header support for A/B recovery layoutZheng Bao2022-03-274-12/+62
| | | | | | | | | | | | | | | | Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* util/amdfwtool: add MSMU, SPIROM_CFG and DMCUB PSP FW typesFelix Held2022-03-273-0/+15
| | | | | | | | | | | | Compared to Cezanne, the Sabrina SoC has a 3 additional PSP firmware table entries, so add those as a preparation for Sabrina support. Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaa5aacd53b3c7637f6d5e94b1a8d92bba57ddb9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/lint/checkpatch: Update commit message & subject line limitsMartin Roth2022-03-251-6/+15
| | | | | | | | | | | | | | | | | The commit message has a (soft) line length limit of 72 characters and the subject has a (soft) line limit of 65 characters. This change updates checkpatch to warn at those limits. Note that neither of these are hard limits because git & gerrit can both handle longer lines, it just doesn't look good. Change-Id: I4ef131a65254e2b184b05e0215969aef97e12712 Signed-off-by: Martin Roth <martin@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* amdfwtool: Change the some FW's level for A/B recoveryZheng Bao2022-03-231-3/+3
| | | | | | | | | | | | | | | | | | The Pubkey(0), PSP bootloader(1) and IKEK(0x21) should be put to level 2 only for A/B recovery for Sabrina, which is going to be the long term and A/B recovery layout only. So the amdfwtool should be changed for Sabrina. The old levels of these 3 FWs are for Cezanne, which doesn't use AB recovery now. Just set the specific field levels in generic Cezanne folder for demo. Leave the fw.cfg in Guybrush unchanged. Change-Id: I11092b52927b2c526a5be719104ba39a790b6fa8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* util/spd_tools: Add support for exclusive IDsRobert Zieba2022-03-222-17/+62
| | | | | | | | | | | | | | | | | Currently memory parts that use the same SPD are assigned the same ID by spd_tools. This commit adds support for exclusive IDs. When given an exclusive ID a memory part will not share its ID with other parts unless they also have the same exclusive ID. BUG=b:225161910 TEST=Ran part_id_gen and checked that exclusive IDs work correctly and that the current behavior still works in their abscence. Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util/cbmem: Keep original Total Time calculation when no negative timestampsBora Guvendik2022-03-211-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "Total time" calculation changed after CL 59555 to include "1st timestamp" value in the calculation. This patch restores original Total Time calculation where "1st timetamp" is subtracted from "jumping to kernel". If pre CPU reset timestamps are added (negative timestamps), "Total time" calculation still includes the pre-reset time as expected. 1) Before https://review.coreboot.org/c/coreboot/+/59555: 0:1st timestamp 225,897 1101:jumping to kernel 1,238,218 (16,316) Total Time: 1,012,281 2) After https://review.coreboot.org/c/coreboot/+/59555: 0:1st timestamp 225,897 1101:jumping to kernel 1,238,218 (16,316) Total Time: 1,238,178 3) After this patch: 0:1st timestamp 225,897 (0) 1101:jumping to kernel 1,238,218 (16,316) Total Time: 1,012,281 BUG=none TEST=Boot to OS, check cbmem -t on Redrix board Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I0442f796b03731df3b869aea32d40ed94cabdce0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* amdfwtool: Check the length of matching string before accessingZheng Bao2022-03-211-10/+21
| | | | | | | | | | | | If AB recovery is enabled and get a "Lx" in fw.cfg, wrong character is got or access violation happens. Change-Id: Ibd8ffe34fd44d860ec2115cd36117da7b02169cd Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* util/liveiso: Remove coreboot toolchain from todoFelix Singer2022-03-171-1/+0
| | | | | | | | | | | | | | | | | | The coreboot toolchain is a huge blob and increases the size of the build a lot. If needed, the specific toolchain can be added before building the ISO or with `nix-shell` later in the live system, as shown below. $ nix-shell -p coreboot-toolchain.i386 Thus, remove this from the todo list. Change-Id: Ia24ceb84f202828f1c97d3ba5bafbf6af0361bdb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* util/ifdtool: Add Meteor Lake platform support under IFDv2Subrata Banik2022-03-152-0/+6
| | | | | | | | | | | | BUG=b:224325352 TEST=Able to build ifdtool. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3564efa27d0271286435284e745458aada987008 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* cbmem: Fix console banner matchesJulius Werner2022-03-101-3/+4
| | | | | | | | | | | | | | | | | | | | | Since the new loglevel markers were added, there will now be a marker character at the beginning of the coreboot banner string, and this will make the existing regular expressions meant to find it fail to match. This patch fixes the problem by just allowing for a single extra character there (any character to avoid the hassle of having to match the marker explicitly). The extra character is optional so that we will still continue to match banners from older versions of coreboot as well. Since the `?` glyph is not available in basic POSIX regular expressions, we have to switch to REG_EXTENDED syntax (should otherwise make no difference). (Also, move side effects out of assert() while I'm here, that's not actually safe for the standard libc implementation.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I99fb347eb1cf7b043a2113dfda7c798d6ee38975 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62720 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/futility: Don't echo the warning message unless it failsMartin Roth2022-03-091-1/+1
| | | | | | | | | | | | | Currently, all of the commands for building futility are printed as they are run. This change skips printing the check for libcrypto unless the check actually fails. This prevents the error from being displayed when there isn't actually a problem. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I9ef36c0b64f7cd69d19b8faabd165ef6651c838e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* cbfstool/linux_trampoline: Fill the ACPI RSDP entryArthur Heymans2022-03-092-9/+22
| | | | | | | | | | | | | | | | | | | | | | | | With LinuxBoot Linux relied on the legacy method of fetching the RSDP pointer to get ACPI. This uses a more modern approach available since 2018 on the Linux kernel, which involves filling in the zero page. This method takes precedence over any other method of fetching the RSDP in Linux (UEFI, Kexec, Legacy/BIOS). Some UEFI zealots are threatening that legacy code will be removed from Linux so it's best to already adapt to that possibility. Tested on Qemu: - With qemu the RSDP is always in the EBDA, so checking if Linux uses the provided pointer is better done with a forced bad entry - With a fake bad pointer Linux correctly does not find RDSP Change-Id: I688b94608b03b0177c42d2834c7e3beb802ae686 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* amdfwtool: Clear struct match before regular expression matchingZheng Bao2022-03-091-5/+19
| | | | | | | | | | | | | | | | If it is not cleared and the number of strings is fewer than last iteration, the match[3] will keep the last value, which actually should be empty. Add assert to make sure the level is a legal value. BUG=b:222038278 Change-Id: If14e0923fbb1648d83784eb5dc1411c93227db5a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* commonlib/bsd: Remove cb_err_tJulius Werner2022-03-091-4/+4
| | | | | | | | | | | | | | | | | cb_err_t was meant to be used in place of `enum cb_err` in all situations, but the choice to use a typedef here seems to be controversial. We should not be arbitrarily using two different identifiers for the same thing across the codebase, so since there are no use cases for serializing enum cb_err at the moment (which would be the primary reason to typedef a fixed-width integer instead), remove cb_err_t again for now. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/spd_tools: Encode SDRAM min cycle time (TCKMinPs)Karthikeyan Ramasubramanian2022-03-081-10/+36
| | | | | | | | | | | | | | | ADL encodes CK cycle time as tCKMin whereas Sabrina encodes WCK cycle time. Encode tCKMin as per the respective advisories. BUG=None TEST=Generate the SPD and ensure that tCKMin is encoded accordingly. Minimum CAS Latency time is also impacted and is encoded accordingly. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I99ada7ead3a75befb0f934af871eecc060adcb26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* util/ifdtool: Add support for Denverton SoCJeff Daly2022-03-082-11/+73
| | | | | | | | | | | | | | | | Denverton is a special version of IFD2 flash layout. It defines 10GbE firmware regions (11/12) and the IE (10) region which other IFD2 platforms do not have. Denverton does not include the legacy GbE region (3) or the EC region (8) which other IFD2 platforms do have. TEST='ifdtool -p dnv coreboot.rom' and verify correct output Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: I15939ce4672123f39a807d63c13ba7df98c57523 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/docker/coreboot-jenkins-node: Alphabetize installed toolsMartin Roth2022-03-021-10/+21
| | | | | | | | | | | | | | It's easier to read and to add new packages when each package is on its own line and they're sorted alphabetically. Indenting them also makes it easier to see what's getting installed and what's a command. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ibfe297bd408ed0783fcff09c1ecb5672fe785c48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62446 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/docker/coreboot-jenkins-node: add linkcheckerMartin Roth2022-03-021-0/+1
| | | | | | | | | | | | The linkchecker tool is now being used to find broken links in our websites. Since it's not needed for building anything, just add it to the jenkins-node Dockerfile instead. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iac2246b5378e556b5cd9f2107fc5a7e51d583b5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62445 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* utils/cbfstool: Fix building with `make test-tools`Felix Singer2022-02-271-11/+13
| | | | | | | | | | | | | | The variable `RM` is empty and thus set it to `rm`. While executing the `clean` rule, run each `rm` command with the -f flag to ignore non-existing files. Also, disable the objutil feature locally fixing another build issue. Change-Id: Icb17e2c924ef480f8ac6195f96cf495709a0a023 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62415 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/testing: Add cbfstool tools to tested utilsMartin Roth2022-02-271-0/+1
| | | | | | | | | | | | Previously, cbfstool was tested as part of the coreboot build, but not tested individually. This let a change that broke elogtool slip through. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I9e7b7a01d4a77ffdac932ba5af12cbd1ba96628b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* Revert "util/cbfstool: Port elogtool to libflashrom"4.164.16_branchMartin Roth2022-02-264-254/+11
| | | | | | | | | | | | | | | | | | | | This reverts commit d74b8d9c990780ba64515b36aaff79d719d71ead. This change breaks the 'make all' build of the cbfstool tools from the util/cbfstool directory unless libflashrom-dev is installed, complaining that flashrom is not installed. Even with libflashrom-dev installed, it breaks building elogtool with the public version of libflashrom-dev. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I572daa0c0f3998e20a8ed76df21228fdbb384baf Reviewed-on: https://review.coreboot.org/c/coreboot/+/62404 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* crossgcc: Upgrade LLVM/clang from 12.0.0 to 13.0.1Elyes HAOUAS2022-02-259-5/+5
| | | | | | | | | | Build/run not tested on board. Change-Id: I8c550d3528a5b1c891b318c08ecfba3a9255e69c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59400 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* amdfwtool: Check the real length of PMU stringZheng Bao2022-02-241-0/+3
| | | | | | | | | | | The length should be checked before the PMU_STR_INS_INDEX(th) character is accessed, otherwise it is going to an access violation. Change-Id: I8b59eb34e1cb01fd6e2571fcebc28ef2084b6ec4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* util/nixshell: Add a Nix shell for building documentationFelix Singer2022-02-221-0/+13
| | | | | | | | | | Add a Nix shell config allowing to build the coreboot documentation. Change-Id: I1c9715c677342241b78fbdef0afeb4536f48d50f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* amdfwtool: Add entries for PMUI & PMUD with instance 2Zheng Bao2022-02-211-0/+4
| | | | | | | | | | Change-Id: I69c4b3cdd2473655064d1329d5319cffdba2425a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
* amdfwtool: Add support for AMD's BIOS A/B recovery featureZheng Bao2022-02-213-75/+217
| | | | | | | | | | | | | | | | | | | | | The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUDZheng Bao2022-02-211-30/+11
| | | | | | | | | | | Add the information of substance and instance in the string for PMUI and PMUD. It is amdfwtool's job to extract the number from the string. Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* util/liveiso: Use programs.flashrom.enableFelix Singer2022-02-212-4/+3
| | | | | | | | | | | | | NixOS 21.11 introduced the option `programs.flashrom.enable`. The option allows installing flashrom and hooking up its udev rules. Thus, set it to `true` and add the user `user` to the `flashrom` group allowing it to use the programmers. Change-Id: I017ddb4314702a5252dfc0d05cd1e4961043d23b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* crossgcc: Upgrade CMake to 3.22.2 versionElyes HAOUAS2022-02-213-2/+2
| | | | | | | | Change-Id: I4272f72dd6ed686dbad5615a0ab44c8c632b5930 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* util/spd_tools/spd_gen/lp5: Encode Bank ArchitectureKarthikeyan Ramasubramanian2022-02-171-19/+106
| | | | | | | | | | | | | | | | ADL supports 8B Bank Architecture, whereas Sabrina supports either BG or 16B Bank Architectures depending on the speed. This influences SDRAM Density and Banks, SDRAM Addressing bytes in SPD. Encode them as per the individual SoC advisories. BUG=b:211510456 TEST=Generate SPDs for Sabrina. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ic854ccccb2b301e75d0f28cd36daf87fd41e07e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* util/spd_tools/spd_gen/lp5: Encode Optional SDRAM featuresKarthikeyan Ramasubramanian2022-02-171-34/+69
| | | | | | | | | | | | | | | | | ADL and Sabrina provide different advisories to encode Optional SDRAM features (byte indices 7 & 9). Encode those bytes as per the respective advisories. BUG=b:211510456 TEST=Generate the SPD binaries for Sabrina. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Icac8ae148458162768a919d9690d7bf96734e6c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* util/chromeos/crosfirmware: format with shfmtMatt DeVillier2022-02-151-44/+38
| | | | | | | | | | Clean up formatting using shfmt Change-Id: I46ce84668bfb4ea3df179317e2848b6bb75d8d5c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* util/amdtools/README,description.md: add update_efs_spi_speed docsFelix Held2022-02-152-0/+5
| | | | | | | | | | | This change is mostly from CB:56644 patchset 3. Signed-off-by: Martin Roth <martin@coreboot.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idece950bab260a099c9790485805cbe8ea641666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/amdtools/description.md: add description for the different toolsFelix Held2022-02-151-1/+10
| | | | | | | | | | | | This change is mostly from CB:56644 patchset 3. Signed-off-by: Martin Roth <martin@coreboot.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4cb9bbb3d7fd5d7c9e33fbf656301c0beb2f1b47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/amdtools/README: convert to markdownFelix Held2022-02-152-31/+27
| | | | | | | | | | | | This change is mostly from CB:56644 patchset 3. Signed-off-by: Martin Roth <martin@coreboot.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idcee9de9bc409a4dfe7d2f8c18ec5132f2747c33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-12 16:04:06 +0000