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* util/docker: Update dockerfilesMartin Roth2022-05-313-8/+18
| | | | | | | | | | | | | | | | - Remove deprecated "MAINTAINER" lines - Add Sphinx tools to coreboot-jenkins-node to check documentation. - Add mdl to check markdown - Alphabetize packages in docs Dockerfile - Add jinja2 version 3.0.3 to the docs Dockerfile - The latest version breaks with the error: "exception: cannot import name 'contextfunction' from 'jinja2'" Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia1de62621a6aef4ecd055a1a3afbebad34448002 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* util: Update description filesMartin Roth2022-05-3010-24/+28
| | | | | | | | | | | | | | | - Spelling fix - Add languages - Update formatting - Move notes that shouldn't be in the description file to a README Change-Id: I4af37327d5834f8546a3f967585658fb5686f17a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* util: Fix a few spelling mistakesMartin Roth2022-05-305-7/+7
| | | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib6f0232292c9e289ee1e87998493ea70beea8e78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* Documentation: Move intelp2m from description.md to DocumentionMartin Roth2022-05-302-177/+2
| | | | | | | | | | | | | The description.md file for the intelp2m utility wasn't the description that was needed - just a subject, and what language it was written in. It was instead a set of more full documentation, so move it into the Documentation directory and create a new description file. Change-Id: Ia180ae41f91f8b8eb408351a9e44e899edc031d3 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* util/lint/checkpatch: Add alloc functions to alloc with multiplies checkElyes Haouas2022-05-291-3/+5
| | | | | | | | | | This reduce difference with linux v5.18. Change-Id: Id9412f7b6c0b9f76b39a094142aaded5c2aa1059 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* util/lint/checkpatch: Update 'Check for compiler attributes'Elyes Haouas2022-05-291-29/+59
| | | | | | | | | | This reduce difference with linux v5.18. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I817630321587dec515cd94aa7b73a17819526190 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* util/lint/checkpatch.pl: Use 'allocFunctions'Elyes Haouas2022-05-291-3/+14
| | | | | | | | | | This reduce difference with linux v5.18. Change-Id: I1fc71b9cb6a4e4f8b27fbe6d45f4fa4e2c236157 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* util/inteltool: Add support for Alder Lake chips detection and GPIOsMichał Kopeć2022-05-286-0/+807
| | | | | | | | | | | | | | Add PCI IDs for Alder Lake H devices and their GPIO tables. PCI IDs as per Intel PCH-H EDS Vol1 (doc #619362). TEST=dump GPIOs on i5-12600K with Z690 chipset Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* abuild: Build with clang only when supportedArthur Heymans2022-05-281-1/+11
| | | | | | | | | | | This changes the behavior of '-L/--clang' to only buildtest when a target has ARCH_SUPPORTS_CLANG set. Change-Id: I362fcd0f795d27f13dde793a79774f08c497bd38 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* util/lint/checkpatch: Warn on period at the end of commit subjectMartin Roth2022-05-281-0/+5
| | | | | | | | | | | | This gives a warning when there's a period at the end of the commit subject line. Change-Id: If95bef3ba01e0ac13ce18045928081040abef4fd Signed-off-by: Martin Roth <martin@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* util/lint: Subtract the patch format string from subject lengthMartin Roth2022-05-281-3/+3
| | | | | | | | | | | | | | Checkpatch was looking for a 65 character length, but format-patch adds the text "Subject: [PATCH] " before the actual subject. Checkpatch needs to account for that when looking at the line length. Lines 2863 & 2864 have their indentation fixed as well. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2f2ee6e0f1b14ae6393ed7e64ba1266aa9debc7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* util/lint: Add commit message parsing to checkpatch_json scriptMartin Roth2022-05-281-0/+6
| | | | | | | | | | | | | | | The commit message wasn't being parsed because there's no filename associated with it in the patch output. This change adds the "filename" for the commit message in Gerrit for any errors that have a line number but no filename. calculations is intentionally misspelled as cacluations as a test. Change-Id: Ie7a2ef06419c7090c8e44b3b734b1edf966597cc Signed-off-by: Martin Roth <martin@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* util/intelp2m: Add support for Alder Lake macro generationMichał Kopeć2022-05-256-2/+150
| | | | | | | | | | | | | | Add support for Alder Lake as a separate parsing profile, copying the existing 'Cannon' profile and adjusting for differences in reset mapping and GPIO macro generation. TEST=Generate GPIO macros for MSI PRO Z690-A Change-Id: I5871394bcb0636c2c803607ffb129441aa934417 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
* util/lint/checkpatch.pl: Reduce difference with linux v5.18Elyes Haouas2022-05-241-49/+82
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id5eb4823399088746a34721a9855bbaf5f97b7b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* Allow trailing whitespaces in .md filesMaximilian Brune2022-05-161-1/+1
| | | | | | | | | | Two trailing whitesspaces have an actual meaning in Markdown files (a new line). Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ibdb92ee857ee4ad32b6afb84ace427b27b41bb7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* util/testing: Remove amdfwread from makefileRobert Zieba2022-05-161-1/+0
| | | | | | | | | | | | | | | | | | | amdfwread was added to the testing makefile but ended up not becoming a separate tool. This commit removes it from the makefile so that `make distclean` works again. Fixes: 29bc79fddb62c30caa33474ac773ae6a6ec1c4f0 ("util/amdfwtool: Add amdfwread utility") TEST=Ran `make distclean` Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I2c8b920bc69d6c20558a28515c52a1e9cecebe27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64348 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/inteltool: Add support for Gemini LakeSean Rhodes2022-05-166-0/+324
| | | | | | | | | | | | Tested on: * StarLite Mk III (N5000) * StarLite Mk IV (N5030) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0ef7619c04db66ea0c6e179bdf0a58ed1ab61a48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/lint/lint-stable-019: Update grep '\s' to [[:blank:]]Martin Roth2022-05-161-1/+1
| | | | | | | | | | | | | | | For some reason, the '\s' syntax is causing an error for me under freebsd. It's entirely possible that I'm doing something wrong, but this change should be fine regardless. Freebsd's grep, GNU grep, and git grep all handle posix regex classes, so this change should be transparent. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I489ec13b4ea2e9c17692888e42b8741763b1a2c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* util/lint/checkpatch.pl: Fix "uninitialized value" error messageElyes Haouas2022-05-161-1/+1
| | | | | | | | Change-Id: I74807f240779060158c6769f63a6e9438a6e5fbe Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* util/lint/checkpatch.pl: Fix "Invalid color mode" error messageElyes Haouas2022-05-161-12/+0
| | | | | | | | | | | | | | | | | | | | | Remove duplicated code: "if ($color =~ /^[01]$/) { $color = !$color; } elsif ($color =~ /^always$/i) { $color = 1; } elsif ($color =~ /^never$/i) { $color = 0; } elsif ($color =~ /^auto$/i) { $color = (-t STDOUT); } else { die "$P: Invalid color mode: $color\n"; }" Change-Id: I5713c364edea806e58df26c3a37b4bba7603ed0a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* util/amdfwtool: Add amdfwread utilityRobert Zieba2022-05-136-38/+286
| | | | | | | | | | | | | | | | | | Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* xcompile,clang: increase the number of bracket-depth for CPPArthur Heymans2022-05-131-0/+1
| | | | | | | | | | | | Clang has a limit for the number of nested brackets in CPP. For soc/intel/common/block/include/intelblocks this is a problem as it largely exceeds the default limit of 256. Change-Id: I93038f918e07f735394fc495a8ed7371cc5b1569 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62175 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool: Add IKEK key for Trusted ApplicationKarthikeyan Ramasubramanian2022-05-053-0/+5
| | | | | | | | | | | | | | | This binary file is required for use by Trusted Applications that execute in PSP. BUG=b:229947314 TEST=Build and boot to OS in Skyrim. Change-Id: I2d05792cfd98fa9c38f5deef1ac3282625983eeb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* cbfstool: MediaTek: Hash bootblock.bin for CBFS_VERIFICATIONYu-Ping Wu2022-05-051-0/+96
| | | | | | | | | | | | | | | | | | | | | MediaTek's bootROM expects a SHA256 of the bootblock data at the end of bootblock.bin (see util/mtkheader/gen-bl-img.py). To support CBFS verification (CONFIG_CBFS_VERIFICATION) on MediaTek platforms, we need to re-generate the hash whenever a file is added to or removed from CBFS. BUG=b:229670703 TEST=sudo emerge coreboot-utils TEST=emerge-corsola coreboot chromeos-bootimage TEST=Kingler booted with CONFIG_CBFS_VERIFICATION=y Change-Id: Iaf5900df605899af699b25266e87b5d557c4e830 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63925 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/scripts: Add options to update_submodulesMartin Roth2022-05-041-42/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | This extends and adds various options to the update_submodules script. Extensions: - Add help text - Add all options, but specifically allow a single repo to be specified, along with a minimum number of changes instead of being fixed at 10. - Make it a more formal script with main() and functions - Show changes in commit message, unless there are > 65 commits. Options: -c | --changes <#> Specify the minimum number of changes to update a repo -h | --help Print usage and exit -R | --repo <dir> Specify a single repo directory to update -s | --skipsync Assume that repos are already synced -V | --version Print the version and exit This does not fix style issues in the original, which will be fixed in a follow-on commit. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I222103babff7d5f4f8eb02869c598a4e06748a17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* utils/cbfstool: Disable Wstrict-prototypes warningManoj Gupta2022-05-021-1/+3
| | | | | | | | | | | | | | | | | As recommended on crrev.com/c/3612466 lz4 code is not supposed to be modified. Since both gcc and clang complain about functions without explicit void in argument with Wstrict-prototypes, just disable it instead instead of enabling. BUG=b:230345382 TEST=llvm tot test BRANCH=none Signed-off-by: Manoj Gupta <manojgupta@google.com> Change-Id: I9f3ae01821447f43b4082598dd618d9f8325dca2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63936 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/cbmem: fix an unused parameter issue in timestamp_getNick Vaccaro2022-04-271-0/+2
| | | | | | | | | | | | | | Fix an unused parameter error when building on devices where __i386__ and __x86_64__ are not defined. BUG=none TEST=none Change-Id: I6c04c8e7b931565c87d358aac1025ebcb7617b13 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63880 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* amdfwtool: Use command line option use-combo to decide if use comboZheng Bao2022-04-252-14/+19
| | | | | | | | | | | | The macro PSP_COMBO is removed and instead use the flag use_combo. As long as this flag is false, the amdfwtool behaves the same way as the macro does. Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Change the name of macros for 'BHD'Zheng Bao2022-04-252-10/+10
| | | | | | | | | | | | | Use BHD instead of BDT as the name of cookie macro. Use L2 to make it clear it is for level 2. The 'BHD2' is misleading, which is going to be used for combo entry. The definition in psp_verstage is also changed. Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cpu/x86/64bit: Generate static page tables from an assembly fileArthur Heymans2022-04-253-178/+0
| | | | | | | | | | | | | | | This removes the need for a tool to generate simple identity pages. Future patches will link this page table directly into the stages on some platforms so having an assembly file makes a lot of sense. This also optimizes the size of the page of each 4K page by placing the PDPE_table below the PDE. Change-Id: Ia1e31b701a2584268c85d327bf139953213899e3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/lint/checkpatch.pl: Update lines related to CONST_STRUCTElyes Haouas2022-04-241-4/+7
| | | | | | | | | | Update to v5.18-2 version. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I0fe2ec6a74a4b8c70452fbf05d534a37e1ea2c26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
* util/lint/checkpatch.pl: Add strlcpy checkElyes Haouas2022-04-241-0/+6
| | | | | | | | | | Update to v5.18-2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ic4eaa3f26bcd60ea509a52d5715c7ce1f43b6d3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
* util/lint/checkpatch.pl: Update C99_COMMENT_TOLERANCE linesElyes Haouas2022-04-241-1/+2
| | | | | | | | | | Update to v5.18-2 version. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: If230fa5cd01ab3ce91d8c910667c3d609cf978b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
* util/lint/checkpatch.pl: Update TYPECAST_INT_CONSTANT linesElyes Haouas2022-04-241-10/+10
| | | | | | | | | | Update to v5.18-2 version. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I8ed89e53f647b1b071abff33a434fb3b8dbb1de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
* util/lint/checkpatch.pl: Update the check of repeated wordsElyes Haouas2022-04-241-0/+62
| | | | | | | | | | Update to v5.18-2 version. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I7f5e597bb76e1b9feeb2d6ea290626f45e9fe6c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
* lint/checkpatch.pl: Update to v5.18-2 lines related to "CONFIG_"Elyes Haouas2022-04-241-53/+89
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I8589d053871ad9ac64ae2f8fc380710be8e4556b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
* util/lint/checkpatch.pl: Update lines related to max_line_lengthElyes Haouas2022-04-241-4/+8
| | | | | | | | | | Upadate to v5.18-2 version. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ib9927bfa98e20d4b621bf7abecec234b4754ee9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
* util/lint/checkpatch.pl: Update lines related to tabsizeElyes Haouas2022-04-241-0/+5
| | | | | | | | | | Update to v5.18-2 version. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I6651a3f8e79beca2e1235fe8de3217875f81ba2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
* util/lint/checkpatch.pl: Update to v5.18-2 lines related to verbosityElyes Haouas2022-04-241-7/+95
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I66f38cb01e58ee241bf58c4db83693029ddebcfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/63437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
* util/cbmem: add an option to append timestampMattias Nissler2022-04-221-7/+96
| | | | | | | | | | | | | | | | | | Add an option to the cbmem utility that can be used to append an entry to the cbmem timestamp table from userspace. This is useful for bookkeeping of post-coreboot timing information while still being able to use cbmem-based tooling for processing the generated data. BUG=b:217638034 BRANCH=none TEST=Manual: cbmem -a 1234 to append timestamp, verify that cbmem -t shows the added timestamp. Change-Id: Ic99e5a11d8cc3f9fffae8eaf2787652105cf4842 Signed-off-by: Mattias Nissler <mnissler@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* coreboot_tables: Replace 'struct lb_uint64' with lb_uint64_tJianjun Wang2022-04-143-30/+8
| | | | | | | | | | | | | | | Replace 'struct lb_uint64' with 'typedef __aligned(4) uint64_t lb_uint64_t', and remove unpack_lb64/pack_lb64 functions since it's no longer needed. Also replace 'struct cbuint64' with 'cb_uint64_t' and remove 'cb_unpack64' in libpayload for compatible with lb_uint64_t. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* util/apcb/apcb_v3_edit.py: Edit APCB based on different SPD magicKarthikeyan Ramasubramanian2022-04-141-2/+14
| | | | | | | | | | | | | | | | | APCB edit tool edits APCBs with LP4 specific SPDs. Introduce an option to support different SPD magic so that the tool can be used to edit APCBs with LP5 specific SPDs. BUG=None TEST=Build Skyrim board with LP5 specific SPDs. Build Guybrush board with LP4 specific SPDs. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I8e96c89e4e5ce8e0567a17bf7685b69080fa1708 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63598 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/spd_tools/part_id_gen: Support Sabrina SoCKarthikeyan Ramasubramanian2022-04-141-0/+1
| | | | | | | | | | | | | | Add support to generate DRAM part ID for boards using Sabrina SoC. BUG=None TEST=Generate DRAM part ID for Skyrim mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ica57b12239019831f7bf93982be3c93b7f8b6986 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/amdfwtool: Maintain one copy of PSP Level2 entriesKarthikeyan Ramasubramanian2022-04-142-4/+20
| | | | | | | | | | | | | | | | | | | | | | | AMDFWtool maintains 2 copies of PSP Level2 entries - one in primary slot A (Type 0x48) and another in backup slot B (Type 0x4A). On boards which use VBOOT with 2 RW firmware slots, maintaining 2 copies of PSP Level2 entries in each FW slot is redundant and space-consuming. Introduce option to maintain only one copy of PSP Level2 entries and point to it from both slots A & B. BUG=None TEST=Build and boot to OS in Skyrim. Ensure that only one copy is added to each FW slot. This achieved a space saving of 1.5 MB in each FW slot. Before: apu/amdfw 0x415fc0 raw 3043328 none After: apu/amdfw 0x415fc0 raw 1556480 none Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Add a flag to record the second gen instead of romsigZheng Bao2022-04-132-13/+38
| | | | | | | | | | | | This is for future feature combo, which gets the soc id from fw.cfg in a loop instead of the command line, and the romsig is not set until fw.cfg is processed. Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* util/lint/checkpatch.pl: Update to v5.18-2 lines related to "codespell"Elyes Haouas2022-04-111-4/+47
| | | | | | | | Change-Id: I55cc4255ea88723c813a04d87e4c028c64f92dbd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* superiotool/ite: add IT8625E EC registersMichał Kopeć2022-04-061-0/+37
| | | | | | | | | | | | | | Add support for dumping ITE IT8625E Environmental Controller registers. Values as per "IT8625E Preliminary Specification V0.3 (For D Version)". Change-Id: I68aad90097206c6b8ef40075530c00809d9511e2 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* amdfwtool: Add a macro to set explicitly second gen for old SOCsZheng Bao2022-04-052-1/+6
| | | | | | | | | | | | It is more reasonable than getting the value from memset. For the reserved bits, keep them as they were for old SOCs. Change-Id: I65caa11e835d2ff52bec4b8904057bbced434891 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* util/spd_tools: Add ability to override SPD file for partsRobert Zieba2022-04-052-27/+64
| | | | | | | | | | | | | | | This commit adds the ability to override the SPD file that is used for a specific part. BUG=b:224884904 TEST=Verified that generated makefile uses specified SPD file and that it remains unchanged when this capability is not used Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I078dd04fead2bf19f53bc6ca8295187d439adc20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* crossgcc: Upgrade IASL from 20211217 to 20220331Elyes Haouas2022-04-044-2/+2
| | | | | | | | | | | | | "REDUNDANT_OFFSET_REMARK" to ignore redundant offset remarks is not needed any more as it’s included upstream. Changes: https://acpica.org/node/199 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ice7f9a10051f7f62c53098161fd2f498d724c17d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-23 23:25:22 +0000