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* inteltool/gpio: Add support for new Lewisburg chipsetsMaxim Polyakov2020-07-213-0/+18
| | | | | | | | | | | | | | | - Add SKUs and Super SKUs of new Lewisburg series chipsets: C621A, C627A, C629A [1]. - These changes allow the utility to generate the GPIO config registers dump. [1] https://review.coreboot.org/c/coreboot/+/40395 Change-Id: I9b63c0a3860a901e58af0c0d5184361661bab5e3 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43534 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/inteltool: add missing L0 and L1 pads for LewisburgMaxim Polyakov2020-07-211-0/+7
| | | | | | | | | | | | | | | The description for L0 and L1 was missed in the datasheet, however, configuration registers for these pads are present. In addition, the chipset contains the "GPP_L0/CSME_INTR_IN" and "GPP_L1/CSME_INTR_OUT" pads in a circuit diagram. Use all available information to add a description for the missed pads. Change-Id: I7a0488c26b3df9de1adc037d94ae290837d65dd8 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40044 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/mb/google: add template files for dalboz and trembylePaul Fagerburg2020-07-1516-0/+131
| | | | | | | | | | | | | | Now that Zork is using upstream coreboot, we need the template files in the main branch. BUG=b:157570490 TEST=n/a Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: I6cab4ab0b414473e0a759dce81df9872a40d3f26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43419 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/board-status: Reject logs with unknown timestampsPaul Menzel2020-07-151-0/+6
| | | | | | | | | | | Check the output of `cbmem -t` for unknown timestamps. If present, ask the user to rebuild `cbmem`. Change-Id: Ief7aa1a698f10d9721964ad1bee057fcd9f4aa40 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* util/intelmetool: Fix error messageEvgeny Zinoviev2020-07-151-1/+1
| | | | | | | | | | | Add a missing space to the message. Change-Id: I7d4042ebb587af8558294fb4961100b43910fd4a Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
* util/inteltool: add PCI ID for ICH10DOIdwer Vollering2020-07-096-0/+7
| | | | | | | | Change-Id: I3561679ef50f4c094d2503539074c957f759ecef Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43321 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/xcompile: Look for the host compiler in XGCCPATH, too (and first)Patrick Georgi2020-07-081-1/+18
| | | | | | | | | | | | | | If there's a host compiler in XGCCPATH, it's likely the same relatively-current version we use for coreboot, and it's a well-known quantity, so let's prefer that over alternatives by default. In addition, look for the C++ host compiler as well. Change-Id: If50341df169a476899b5a5ffd4c4fb6d21c3f4ac Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43144 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/crossgcc: Always bootstrap for gcc < 4.9Patrick Georgi2020-07-071-23/+15
| | | | | | | | | | | | | | | Building cbfstool requires at least 4.9 due to optimizer bugs in gcc 3.x to 4.8.x, so let's not work around ancient compilers in our tree but ensure that users get a newer compiler. Closes: https://ticket.coreboot.org/issues/240 Change-Id: I4e0f80e2790514e6a1b5d5de1a373f365df1569c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43143 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/inteltool: Support dumping more BARs on Skylake mobile SoCsBenjamin Doron2020-07-072-1/+9
| | | | | | | | | | | | | | Support dumping MCHBAR, EPBAR, DMIBAR and PCIEXBAR on SKL-U/Y. These chipsets are similar to others supported by the tool. Working on SKL-U. Change-Id: Ic43d54ef189d500701872a56e67781a744990328 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* lp4x: Add new memory parts and generate SPDsDavid Wu2020-07-071-0/+24
| | | | | | | | | | | | | | | | | | This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for TGL: 1. MT53E512M64D4NW-046 WT:E 2. MT53E1G64D8NW-046 WT:E BUG=b:159195585,b:152936481,b:156435028 TEST=build. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If69087e5e189b3e0f70e5f1afbfe3f884173d3b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* pgtblgen: Update comment to match what the code doesPatrick Rudolph2020-07-061-1/+1
| | | | | | | | | Change-Id: Ib87c804b139a96a4173a6f392f0f99a77d32fc01 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* devicetree: Remove weak declarations for opsKyösti Mälkki2020-07-061-3/+10
| | | | | | | | | | | | | | | Make it compulsory to build with all the drivers that are visible in the board devicetree.cb file. Change-Id: Ifb783e2f733d5c65c615e5c1879e3e4c7a83e049 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* util/tmpl/puff: Allow USB2/3 wakeups to (un)plug eventsEdward O'Callaghan2020-07-031-0/+12
| | | | | | | | | | | | | BUG=b:159187889 BRANCH=none TEST=none Change-Id: Ib59108ec42955b5414f76b591cce5073f7dad1a9 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42990 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/futility: Check for pkg-config and libcryptoPatrick Georgi2020-07-011-2/+9
| | | | | | | | | | | | | | | | | | | | | When building a configuration that requires futility (e.g. Chrome OS builds), pkg-config and libcrypto are required. Since vboot's build system isn't the most helpful about it, test ourselves and fail out with some actionable message. Tested: - configs that don't need futility don't test for pkg-config, so it's not required for them. - failing pkg-config test leads to the message - working pkg-config test leads to a successful build Fixes https://ticket.coreboot.org/issues/242 Change-Id: I103ce5115284352e0a3a7fdcf8b427f56ce15ba7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/cbfstool: Defuse vboot's openssl linkingPatrick Georgi2020-07-011-1/+1
| | | | | | | | | | | | | | | | | Vboot determines openssl through pkgconfig, so pointing its build system to /bin/true makes the build not break unless it needs to use valid information about openssl. Vboot's use of openssl is only for some special features, mostly around PKCS key format parsing and not needed by cbfstool. While cbfstool can link vboot, it can't link with openssl because openssl's license is deliberately incompatible with the GPL. Change-Id: Ia3825f9625a1964d7cefc47ab3c3a8250ceefafb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* crossgcc: Upgrade IASL to version 20200528Elyes HAOUAS2020-07-014-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update fixes build issues with host GCC 10. Other changes: https://acpica.org/node/177 https://acpica.org/node/178 https://acpica.org/node/179 https://acpica.org/node/181 acpinames utility removed: "Removed support for the acpinames utility. The acpinames was a simple utility used to populate and display the ACPI namespace without executing any AML code. However, ACPICA now supports executable opcodes outside of control methods. This means that executable AML opcodes such as If and Store opcodes need to be executed during table load. Therefore, acpinames would need to be updated to match the same behavior as the acpiexec utility and since acpiexec can already dump the entire namespace (via the 'namespace' command), we no longer have the need to maintain acpinames." Change-Id: Ibd995561ca53458b04f87cee5693850c0d90d3d6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38907 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ACPI: Drop typedef global_nvs_tKyösti Mälkki2020-06-301-1/+1
| | | | | | | | | | | | Bring all GNVS related initialisation function to global scope to force identical signatures. Followup work is likely to remove some as duplicates. Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add qc_blobs repositoryJulius Werner2020-06-302-1/+2
| | | | | | | | | | | | | | | | | | | This patch adds a separate blobs repository for Qualcomm blobs, analogous to the existing AMD blobs. Qualcomm's binary licenses allow files to be redistributed and used by anyone, but they explicitly require the user to agree to the license terms when just *downloading* the binary (even if they're not using them to build any firmware). Some community members do not like to have to agree to licenses for files they're not actually using, so we are keeping these files separate from the main blobs repository and adding an extra Kconfig to make sure the user is aware of and must explicitly agree to this before downloading these files. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I247746c1b633343064c9f32ef1556000475d6c4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Fix up Docker paths to match jenkins nomenclatureStefan Reinauer2020-06-261-5/+5
| | | | | | | | | | | Jenkins is calling its build nodes "agent". Reflect that in the path names we use in configuration. Change-Id: I88a4d3d32a565ade768e3de6428f46d355bedfb2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42819 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/abuild: Only update submodules oncePatrick Georgi2020-06-251-0/+3
| | | | | | | | | | | | Without this, each build will try to update the submodules. Not necessarily a problem but git locks repos, creating spurious error messages. Change-Id: Iba20677d4b5f9365c92f7ed247ca56acb7d33b27 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/mainboard/google/volteer: Add dptf.asl to the templateZhuohao Lee2020-06-241-0/+3
| | | | | | | | | | | | | | | The dptf.asl is needed when creating a new volteer variant, otherwise, it will make the variant build failed. The error could be found from this link: https://review.coreboot.org/c/coreboot/+/42709 BUG=b:158797761 TEST=Generate the Delbin correctly Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Change-Id: Ib4059df9e08d6a1dba88f0299bb39c8c6ae406ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/42715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* util/mb/google/tmpl/puff: Fix overridetree.cb to swap USB portsEdward O'Callaghan2020-06-231-10/+7
| | | | | | | | | | | | | | | Switch USB2 port1 and port3 due to circuit change from rev0. BUG=b:154071868,b:154585046,b:156429564 BRANCH=none TEST=none Change-Id: I5b9a20bd657ed587ec891e52f66629d554df6166 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* util/mb/google/tmpl/puff: Import overridetree.cb copyEdward O'Callaghan2020-06-231-0/+400
| | | | | | | | | | | | | BUG=b:154071868 BRANCH=none TEST=none Change-Id: I40faa5f80e78cd73ba5ef977574f7f662c0ab8a1 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* util/mb/google/tmpl/puff: Generate correct gpio muxingEdward O'Callaghan2020-06-232-2/+117
| | | | | | | | | | | | | BUG=b:154071868 BRANCH=none TEST=none Change-Id: Iae4fe48b6a3df730b2334cb1f32b35addc90bec0 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* util/mb/google/tmpl/puff: Fix include paths for gen boardEdward O'Callaghan2020-06-232-2/+2
| | | | | | | | | | | | | BUG=b:154071868 BRANCH=none TEST=none Change-Id: Ifa5cd021ae37d61ddb9eb9bf6a970a931058e33c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* src/mainboard: Remove unused include 'sandybridge.h'Elyes HAOUAS2020-06-221-1/+0
| | | | | | | | Change-Id: I9356a56c34d1c6746cf8acfe931386ffed58ba74 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* lint: convert checkpatch_json.py to python 3Stefan Reinauer2020-06-181-5/+5
| | | | | | | | | | | | | | | | Align all coreboot scripts on one python version. Tested by running the original suggested test: $ nice -n 20 git diff HEAD~ | util/lint/checkpatch.pl \ --no-signoff -q - | tee checkpatch.txt $ util/lint/checkpatch_json.py checkpatch.txt \ comment.json checkpatch.txt Change-Id: Iec2bb0be23b27a3eaf92f293c962a8e6bfb03af0 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* crossgcc: Upgrade GDB to version 9.2Elyes HAOUAS2020-06-177-14/+13
| | | | | | | | Change-Id: I30dae356ec3b373ac036c7eced7d6e89ddd08246 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38787 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* crossgcc: Remove "Make"Elyes HAOUAS2020-06-177-138/+5
| | | | | | | | | | | In its current state, it draws more dependencies in than it solves which makes it useless. Change-Id: I08f592731c3da2ac19e1f93682256f559a067fc4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ifdtool: Improve PCH strap handlingPatrick Rudolph2020-06-172-11/+54
| | | | | | | | | | | | | | | | | | | | Read the PCH Strap Length field in FLMAP1 as described in the "SPI Programming Guide" and print the number of fields specified there. This code dumps the following straps: * Intel GM45: 8 straps * Intel C216: 72 straps * Intel C240: 360 straps Add a new function to easily set PCH straps, which is useful for debugging. Change-Id: Ieb7891b214d82c984379794de9b3fe1a6d0d3466 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* sandybridge boards: Factor out MAX_CPUSAngel Pons2020-06-151-2/+0
| | | | | | | | | | Also update autoport accordingly. Change-Id: I12481363cf0e7afc54e2e339504f70632e8d72e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41839 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/cbfstool: Add option --pow2pageKyösti Mälkki2020-06-151-2/+20
| | | | | | | | | | | | For add-stage command, --pow2page is equivalent of passing -P log2ceil(sizeof stage). The sizeof stage can be hard to determine in Makefile to be passed on the commandline. Change-Id: If4b5329c1df5afe49d27ab10220095d747024ad6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* util/board_status: Also check remotely retrieved coreboot console logPaul Menzel2020-06-141-6/+10
| | | | | | | | | | | | | | | Currently, the logs are only checked, if retrieved locally. Moving it after the if statement, now logs retrieved remotely are also checked. The change in behavior is, that now all commands are executed first, so before hitting this error, other errors might occur unrelated to the console log. Change-Id: I016bbde66c58a654042ad880c6007ddc1d143691 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/intelmetool: Add support for Intel Cannon Point LP HECI ControllerMatt DeVillier2020-06-141-0/+2
| | | | | | | | | | Tested on Intel NUC 8i5BEH (CFL) and Purism Librem Mini (WHL) Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I1054455fff2dcae8d17afe2adf3329eb44aa862a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/cbfstool: Drop IS_TOP_ALIGNED_ADDRESS() check in cbfstool_convert_fspFurquan Shaikh2020-06-131-13/+10
| | | | | | | | | | | | | | | | | This change drops the check for IS_TOP_ALIGNED_ADDRESS() before setting offset to 0 in cbfstool_convert_fsp(). If the user provides a baseaddress to relocate the FSP to, then the offset should be set to 0 since there is no requirement on where the file ends up in cbfs. This allows the user to relocate the FSP to an address in lower DRAM. BUG=b:155322763 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ibeadbf06881f7659b2ac7d62d2152636c853fb9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/42263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Revert "util/abuild: Have abuild generate the .xcompile if it doesn't exist"Nico Huber2020-06-101-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 9ff4029db9b1053b44e4fc487243017a099a49c5. Pulling the toplevel Makefile into a tiny one has all sorts of side effects. For instance, the toplevel (random) .config is also included so the results depend on the board that is selected there. What finally broke it is a line that is unconditionally printed for AMD Picasso boards resulting in lots of lines like this: skipping LENOVO_W520 because we're missing compilers for \ (Adding PSP c7ce61492157d3237f679c4a40a08b79 \ .../coreboot/3rdparty/amd_blobs/picasso/PSP/PspBootLoader_prod_RV.sbin) While both issues, the random .config and amd/picasso, could be worked around easily, it seems hard to predict what other pitfalls are lurking in the Makefile inclusion. Also, the problem solved by its inclusion can be fixed by a much simpler `make .xcompile`. Change-Id: I2ff70f561d717eb30e5f3c06c83e83468e174ec5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* util/abuild: Ensure .xcompile existsNico Huber2020-06-101-0/+2
| | | | | | | | | | | | abuild requires the `.xcompile` file to be present already before it runs any actual `make` builds that would generate it. Change-Id: Ib485e7741b7700fa241c192e60900ae5f1d977f5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* templates: remove Dedede and Volteer Makefile.incPaul Fagerburg2020-06-103-10/+0
| | | | | | | | | | | | | | | | | | SPD sources for Dedede and Volteer are being auto-generated by SPD tools now, and so we can remove SPD_SOURCES from Makefile.inc for those templates. That makes Makefile.inc empty for those reference boards, so remove Makefile.inc from the templates. BUG=b:158492307 BRANCH=None TEST=Create new variant of volteer, waddledee, and waddledoo, and verify that we can still build the coreboot image. Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: Iba5264384302300cc8d2256a6b43f3353770154a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42204 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* crossgcc: Backport GNAT exception handler v1 patchIru Cai2020-06-101-0/+270
| | | | | | | | | | | | | | | | | | | | | | | | The GCC 10 GNAT toolchain uses a new exception handler ABI, so older GNAT cannot be built with GCC 10. This patch backports the new exception handler in libgnat to make GNAT able to be built. The libgnat patch doesn't remove the old exception handler, so it can still be built with older compilers. The cross toolchain can now be built with GCC 10.1.0 in Arch Linux (with the latest IASL in CB:38907 that can be built in Arch), and the toolchain can build a working coreboot image with libgfxinit for HP EliteBook 2560p. The original and patched crossgcc built with Debian 10.4 GCC 8.3.0, and the patched crossgcc built with Arch GCC 10.1.0 generate identical coreboot images with `make BUILD_TIMELESS=1`. Change-Id: I757158056bf4698d3c68715e026c226615bc70a1 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42158 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool: Add option for setting PSP/FW shared memory locationMartin Roth2020-06-081-4/+31
| | | | | | | | | | | | | | | | | | | This tells the PSP where in main memory to copy the vboot workbuf. BUG=b:152576063 TEST=Build sharedmem destination into AMDFW, verify shared memory gets placed at that location. Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: Ie1e955e22632ca5cf146ac6eec0407091e81f519 Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2148830 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42044 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool: update to allow building in any locationMartin Roth2020-06-081-16/+31
| | | | | | | | | | | | | | | | | | | | For the verstage-on-PSP implementation, we need 2 additional copies of the AMD firmware tables at non-standard locations. These are for RW-A & RW-B fmap regions. This change allows us to build the AMD firmware tables into those regions. BUG=b:148767300 TEST=boot with psp_verstage, verify boot location Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: I2b591b50e9b179fdfaead46ff93722fa2a155e9c Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2144534 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: I7f841db8617b953dc671a9c12576145f85263581 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* spd/lp4x: Set manufacturer part name to blank (0x20)Furquan Shaikh2020-06-081-0/+15
| | | | | | | | | | | | As per JEDEC spec, manufacturer part name should be set to blank (0x20). This change updates gen_spd.go to set bytes 329-348 as 0x20 and regenerates SPDs for TGL and JSL. Change-Id: I6af18d89afd7264cec7e54b38e95df83d55aa058 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42023 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lp4x: Add new memory parts and generate SPDsFurquan Shaikh2020-06-061-1/+49
| | | | | | | | | | | | | | | | | | This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for TGL and JSL: 1. MT53E512M32D2NP-046 WT:E 2. K4U6E3S4AA-MGCR 3. H9HCNNNCPMMLXR-NEE 4. K4UBE3D4AA-MGCR BUG=b:157862308, b:157732528 Change-Id: Ib7538247d39dfe5faab277d646f87f09103d6969 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41989 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/spd_tools/intel/lp4x: Add a global list of LP4x memory partsFurquan Shaikh2020-06-061-0/+114
| | | | | | | | | | | | | | | | | | This change adds a JSON file (`global_lp4x_mem_parts.json.txt`) containing global list of LP4x memory parts to live along with the spd tools since the part information is not really any SoC or mainboard dependent and comes directly from the part datasheet. It can be shared by mainboards based on different platforms supported by the tools. BUG=b:155239397,b:147321551 Change-Id: I9e2f98fc9c1c8a7f73c9a1bfab22c996de222a32 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41874 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util: Add spd_tools to generate SPDs for TGL and JSL boardsFurquan Shaikh2020-06-063-0/+1450
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Serial Presence Detect (SPD) data for memory modules is used by Memory Reference Code (MRC) for training the memory. This SPD data is typically obtained from part vendors but has to be massaged to format it correctly as per JEDEC and MRC expectations. There have been numerous times in the past where the SPD data used is not always correct. In order to reduce the manual effort of creating SPDs and generating DRAM IDs, this change adds tools for generating SPD files for LPDDR4x memory used in memory down configurations on Intel Tiger Lake (TGL) and Jasper Lake (JSL) based platforms. These tools generate SPDs following JESD209-4C specification and Intel recommendations (doc Two tools are provided: * gen_spd.go: Generates de-duplicated SPD files using a global memory part list provided by the mainboard in JSON format. Additionally, generates a SPD manifest file (in CSV format) with information about what memory part from the global list uses which of the generated SPD files. * gen_part_id.go: Allocates DRAM strap IDs for different LPDDR4x memory parts used by the board. Takes as input list of memory parts used by the board (with one memory part on each line) and the SPD manifest file generated by gen_spd.go. Generates Makefile.inc for integrating the generated SPD files in the coreboot build. BUG=b:155239397,b:147321551 Change-Id: Ia9b64d1d48371ccea1c01630a33a245d90f45214 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util/mb/google: add templates for puff boardsPaul Fagerburg2020-06-045-0/+29
| | | | | | | | | | | | | | Add template directory for the Puff reference board. BUG=b:157701044 BRANCH=None TEST=N/A Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: Ic81c663b92eeb1d39c2b425d331eb16812f58b7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/42026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* util: Allow overriding gcc as default host compilerPatrick Georgi2020-06-042-2/+2
| | | | | | | | | | | | BUG=chromium:1088209 TEST=emerge coreboot-utils (with patches to the ebuild) works Signed-off-by: Patrick Georgi <pgeorgi@google.com> Change-Id: I25d237d048e417f4e412583031905ecf3614c431 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* sconfig: Add support for firmware configurationDuncan Laurie2020-06-027-252/+700
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds support to sconfig for generating the firmware configuration field and option definitions in devicetree.cb. In addition these fields and options can be used to probe for a device and have that device be disabled if it is not found at boot time. New tokens: fw_config: top level token, table can be defined before chips field: define field in the mask with the start and end bits option: define option in a field with the value of the field probe: indicate that a device should probe by field and option Example: fw_config field FEATURE 0 0 option DISABLE 0 option ENABLE 1 end end chip drivers/generic/feature device generic 0 on probe FEATURE ENABLE end end Variants can add new fields and add new options to existing fields in overridetree.cb but cannot redefine an existing option. Devices can have multiple probe tokens, and the device will be considered to be found if any of them return true. The output from defining this field are: 1) the various fields and options will be added as macro constants to static.h and can be used by fw_config for probing. 2) the probe entries will result in a list of fields/options to probe that is added to the resulting struct device and handled by coreboot. BUG=b:147462631 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I8aea63e577d933aea09e0d0b09470929cc96e0de Reviewed-on: https://review.coreboot.org/c/coreboot/+/41440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* util/sconfig: Move default includes out of emit_chips()Nico Huber2020-06-021-3/+3
| | | | | | | | | | | This should make it easier to add more includes. Change-Id: Ib4a25352901408c2b36de4972391df742a0d8037 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41744 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/sconfig: Refactor and fix add_register()Nico Huber2020-06-021-18/+19
| | | | | | | | | | | | | add_register() contained a duplicate check but only compared the new key to the first (smallest in order) list member. Fix that and factor the list handling out so it can be used by other functions. Change-Id: I5a8346f36fa024351e1282c9681868ecf451b283 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41743 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 12:35:53 +0000