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* util/cse_fpt: Add a new tool for managing Intel CSE FPT binariesFurquan Shaikh2021-10-197-2/+715
| | | | | | | | | | | | | This change adds a new tool `cse_fpt` which can be used to print and dump CSE partitions in Flash Partition Table (FPT) format. BUG=b:189167923 Change-Id: I93c8d33e9baa327cbdab918a14f2f7a039953be6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/amdfwtool: rename PSP related embedded_firmware struct elementsFelix Held2021-10-192-5/+5
| | | | | | | | | | | | | | | The element at offset 0x14 in the embedded_firmware struct is the pointer to the combo PSP directory header, so rename it from comboable to combo_psp_directory to clarify that this is not a flag, but a pointer to a data structure. Also rename psp_entry to psp_directory since it points to the PSP directory table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6149c17ae813f4dcea71c308054849a1a2e4394 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* cbfstool: Add helper function `buffer_from_file_aligned_size`Furquan Shaikh2021-10-182-3/+18
| | | | | | | | | | | | | | | This change adds a helper function `buffer_from_file_aligned_size` that loads a file into memory buffer by creating a memory buffer of size rounded up to the provided `size_granularity` parameter. BUG=b:189177186,b:189167923 Change-Id: Iad3430d476abcdad850505ac50e36cd5d5deecb4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* kconfig_lint: Drop overly restrictive rule about choice configsNico Huber2021-10-181-10/+1
| | | | | | | | | | | | | | | | | | | | This rule was creating trouble: * A symbol may only be declared inside or outside a choice. The linter treats every occurence of a `config` entry as a symbol declaration, even when it's just setting a default or adding selects. This is not easy to fix as the symbol objects are not created first and then added to the $symbols array when we know what kind of decla- ration we have, but are created incrementally inside this global list. Change-Id: I48a17f6403470251be6b6d44bb82a8bdcbefe9f6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56410 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* libpayload: Add unit-tests framework and first test caseJakub Czapiga2021-10-181-0/+1
| | | | | | | | | | | | | This commit adds a unit-tests framework ported from coreboot, and test for drivers/speaker. Usage of the unit-tests framework is same as for the coreboot one. Change-Id: Iaa94ee4dcdc3f74af830113813df0e8fb0b31e4f Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mainboard: Drop invalid `VGA_BIOS_FILE` defaultsAngel Pons2021-10-151-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | If the VGA BIOS file path for `VGA_BIOS_FILE` in a mainboard's Kconfig does not exist in the coreboot tree (including submodules), drop it. These files should be stored in the `site-local` subdirectory and the paths specified for each board in `site-local/Kconfig`. For example: config VGA_BIOS_FILE default "site-local/x200_vbios.bin" if BOARD_LENOVO_X200 Note that this is just an example. There are better ways to structure one's `site-local` subfolder. Using the `CONFIG_MAINBOARD_DIR` option would be one of them, though variants may still need special handling. Also, update autoport to not generate `VGA_BIOS_FILE` defaults. Change-Id: I1b5dfba035a42d7943f270f95fb7d32b285584d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* util/autoport/bd82x6x.go: Fix includesNicholas Chin2021-10-121-1/+2
| | | | | | | | | | | | | | Fix include of nvs.h to reflect commit 661ad4666c (ACPI: Select ACPI_SOC_NVS only where suitable); and re-add <device/pci_ops.h>, removed in commit 0aad0531dc (util/autoport/bd82x6x.go: Drop unused includes), as the generated early_init.c uses pci_write_config16(). Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Change-Id: Ic1e97cfa7dce0e4d25f7a37c28d3635bdbf6c2a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* util/cbfstool: Add support for ARM64 UefiPayloadRex-BC Chen2021-10-042-2/+3
| | | | | | | | | | | | | UEFI payload is supported on some ARM64 platforms, for example MT8195. As a result, add MACHINE_TYPE_ARM64 to support ARM SystemReady. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I4c0c6e263bd2f518a62ff9db44d72dd31086756a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* util/liveiso: Install nvme-cli toolFelix Singer2021-10-011-0/+1
| | | | | | | | | | | nvme-cli is used to manage NVMe devices and it supports many vendors. Also, it seems it's commonly used to do firmware updates. Change-Id: I26a78867b01d3af0441827c5b25343a46d7ddea1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* Revert "Revert "util/abuild: Regenerate xcompile on every abuild run""Reka Norman2021-09-261-0/+1
| | | | | | | | | | | | | | | | | | | | This reverts commit d94f8bbe9da290e120df20bf244920436e9510e7. This is a reland of https://review.coreboot.org/57651. The original change broke parallel abuild runs since the xcompile file was deleted by every recursive call to abuild. This issue was fixed by rebasing on top of a change which only regenerates the xcompile on non-recursive calls. BUG=None TEST=Parallel abuild run succeeds. Change-Id: I086ba7b2ae1b8b14459838bd18ce962a84aa306d Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* elogtool: Fix off-by-one error in month in timestampRicardo Quesada2021-09-241-1/+2
| | | | | | | | | | | | | | | | elogtool was setting the timestamp with the wrong value in the month. This CL fixes that by incrementing the month by one. This is needed since gmtime() returns the month value starting at 0. TEST=pytest elogtool_test.py (see next CL in relation chain) Change-Id: I00f89ed99b049caafba2e47feae3c068245f9021 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* util/abuild: Run `make .xcompile` only onceNico Huber2021-09-241-4/+4
| | | | | | | | | | | | | If abuild called itself recursively, the file already exists and we can spare us one evaluation of all the makefiles per recursive abuild run. Change-Id: Id3e2239354ec251c24c03c971987586deeb026c5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* kconfig_lint: restrict definition of defaults for choice elementsMichael Niewöhner2021-09-231-0/+9
| | | | | | | | | | | | | Defining defaults for symbols used inside choices is not allowed. Add a check for this, so we can drop the existent, overly restrictive checks in the follow-up change. Change-Id: I45bce2633dbd168fceb81ceae9b68621b28526e8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Martin Roth <martinroth@google.com>
* util/crossgcc: Update gcc to 11.2Patrick Georgi2021-09-2311-21485/+25
| | | | | | | | | | | Various fixes to gnat and the improved nds32 backend have been merged into gcc by now, so we don't need to carry those patches anymore. Change-Id: Icdee2a8beedd109ee1f0eef6f32f7accbf66674b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* util/spd_tools: Remove old lp4x and ddr4 versions of spd_toolsReka Norman2021-09-239-4115/+0
| | | | | | | | | | | | | | | The migration to the new unified version of spd_tools is complete, so the old lp4x and ddr4 versions can be removed. BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I6b1fc297739efc8dc7d7eec64956bf3343984604 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/spd_tools: Sort platforms_manifest entries by set numberReka Norman2021-09-231-3/+10
| | | | | | | | | | | | | | | Ensure that the order of entries in each platform manifest is consistent every time spd_gen is run. BUG=b:191776301 TEST=Run spd_gen for lp4x and ddr4, check that the manifests are unchanged. Change-Id: I7bfea65c8fc781df80a8725c0cf20c7547c857e8 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/mb/google: Update templates to refer to the new spd_toolsReka Norman2021-09-2314-21/+21
| | | | | | | | | | | | | | | | | Update the new variant templates to refer to the new unified version of spd_tools: - Update the comments in mem_parts_used.txt - Change the placeholder SPD in Makefile.inc to 'placeholder' BUG=b:191776301 TEST=None Change-Id: I03265de0d1182da81dd25a2fe6f940a0b82e5fa4 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* amdfwtool: Add an optional column of levelZheng Bao2021-09-231-6/+79
| | | | | | | | | | | | | | | | | | The value of level defined in table is the default one. We now give an extra option in config file to change this value so some FWs can be dropped in a more optimized way. For the non A/B recovery mode, The value could be L1, L2, Lb or Lx, which are level 1, leve 2, level both and using default value. If it is empty or Lx, left the level in table unchanged. Give a redundant field [12bxBX] in regular exprssion for A/B recovery which will be done later. Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util/spd_tools: Remove PLK platformReka Norman2021-09-233-4/+1
| | | | | | | | | | | | | | | Currently spd_tools treats PCO and PLK as separate platforms. This is unnecessary since they have the same SPD requirements. Remove PLK, and use PCO as the platform for all zork variants. BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I7eeeab53fb3e0d92c3675fb80b4747297d4257ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/57771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util/spd_tools: Add README for unified spd_toolsReka Norman2021-09-231-0/+495
| | | | | | | | | | | | | | | | Combine the existing lp4x and ddr4 READMEs into a single file, and update it to reflect the new unified version of the tools. BUG=b:191776301 TEST=None Change-Id: I866932a1d0b5b6b47b0daff893b37de7a302b4e6 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util/spd_tools: Add 'Generated by' string to part_id_gen output filesReka Norman2021-09-211-6/+10
| | | | | | | | | | | | | | | Add a 'Generated by' string to the generated Makefile.inc and dram_id.generated.txt, showing the command used to generate the files. BUG=b:191776301 TEST=Run part_id_gen, check that the generated files contain the string Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ic9a7826212a732288f36f111b7bc20365a1f702d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
* util/spd_tools: Automatically determine the SPD dir in part_id_genReka Norman2021-09-211-20/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, one of the arguments to part_id_gen is the directory containing the SPD files, e.g. spd/lp4x/set-0. This requires the user of the tool to understand the spd/ directory structure, and manually look up the set number corresponding to their platform. Change part_id_gen to take the platform and memory technology as arguments instead of the SPD directory, and automatically determine the SPD directory by reading the platforms manifest file generated by spd_gen.go. BUG=b:191776301 TEST=Run part_id_gen and check that the generated Makefile.inc and dram_id.generated.txt are the same as before. Example: util/spd_tools/bin/part_id_gen \ ADL \ lp4x \ src/mainboard/google/brya/variants/kano/memory \ src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt Change-Id: I7cd7243d76b5769e8a15daa56b8438274bdd8e96 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/spd_tools: Add max ID check for auto-generated IDs to part_id_genReka Norman2021-09-211-0/+3
| | | | | | | | | | | | | | | | Currently, the maximum part ID of 15 is enforced only for manually assigned IDs. Also enforce it for automatically assigned IDs. BUG=b:191776301 TEST=part_id_gen fails when the number of part IDs which would be assigned is greater than MaxMemoryId. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I802190a13b68439ccbcdb28300ccc5fd1b38a9c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util: Add DDR4 generic SPD for 4JQA-0622ADFrank Wu2021-09-211-0/+11
| | | | | | | | | | | | | | | Add SPD support for DDR4 memory part BUG=b:199469240 TEST=none Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ie67cf6b90304f0bcf80838866c7461c0cea86dc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* Revert "util/abuild: Regenerate xcompile on every abuild run"Reka Norman2021-09-211-1/+0
| | | | | | | | | | | | | | This reverts commit a2c009bd94aa3c9694158f9e28184ccbd94df42b. Reason for revert: Breaks parallel abuilds. Change-Id: I368b189050d519769f4852fea8e255e9b31b27b6 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* elogtool: compile in 32-bit platformsRicardo Quesada2021-09-211-2/+2
| | | | | | | | | | | | | | | | | | This CL fixes a compilation error that happens in 32-bit platforms. This error happens because printf() was using %ld instead of %zu to print size_t variables. This CL fixes it. BUG=b:200608182 TEST=emerge-kevin (ARM 32-bit) TEST=emerge-eve (Intel 64-bit) Change-Id: I340e108361c052601f2b126db45caf2e35ee7ace Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* util/spd_tools: Implement a unified version of the part_id_gen toolReka Norman2021-09-202-1/+315
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently there are two versions of gen_part_id.go, one for LP4x and one DDR4. This change implements a unified version of this tool. The new part_id_gen.go is almost identical to the existing ddr4/gen_part_id.go. The new version was based on the ddr4 version and not the lp4x version, since the ddr4 version contains extra logic to support fixed IDs in the mem_parts_used files. The only non-trivial change from ddr4/gen_part_id.go is to include the full paths of SPD files in the generated Makefile.inc. E.g. instead of SPD_SOURCES += lp4x-spd-1.hex the full path relative to the coreboot root directory is included: SPD_SOURCES += spd/lp4x/set-0/spd-1.hex BUG=b:191776301 TEST=For each variant of brya/volteer/dedede/guybrush/zork, run part_id_gen and verify that the generated Makefile.inc and dram_id.generated.txt are identical to those currently in the src tree, except for the modified SPD file paths in Makefile.inc. Example: util/spd_tools/bin/part_id_gen \ spd/lp4x/set-0 \ src/mainboard/google/brya/variants/kano/memory \ src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt Change-Id: Ib33d09076f340f688519dae7956a2b27af090c0b Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util/abuild: Regenerate xcompile on every abuild runReka Norman2021-09-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, running abuild in a fresh checkout without having built the toolchain results in the following confusing behaviour: 1. Run abuild. It fails due to the missing coreboot toolchain, and the error message suggests running `make crossgcc`. 2. Run `make crossgcc`. It succeeds. 3. Re-run abuild. It still fails due to a missing coreboot toolchain. This happens because the first abuild run generates an xcompile file which uses the system toolchain. The second abuild run doesn't regenerate the xcompile, so it still fails due to the non-coreboot toolchain. To avoid this confusing behaviour, regenerate the xcompile file every time abuild is run. BUG=None TEST=Perform the steps above in a clean checkout. The second abuild run now succeeds. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I78a7702c45cecbfe8460ec55df03741e5ced94b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* sconfig: Emit device structure pointers if alias names are providedFurquan Shaikh2021-09-201-2/+16
| | | | | | | | | | | | | | | | | | This change uses _dev_${ALIAS_NAME} as the name for `struct device` if the device has an alias. In addition to that, it emits _dev_${ALIAS_NAME}_ptr which points to the device structure. This allows developers to directly reference a particular device in the tree using alias name without having to walk the entire path. In later CLs, mainboards are transitioned to use this newly emitted device structure pointers. Change-Id: I8306d9efba8e5ca5c0bda41baac9c90ad8b73ece Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util/crossgcc: Update binutils to 2.37Patrick Georgi2021-09-197-6/+6
| | | | | | | | | Change-Id: Ia68d4d9f836ad23fb8f6a7203a78b4ea40c7c43b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* util/spd_tools: Implement a unified version of the spd_gen toolReka Norman2021-09-175-0/+2483
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently there are two versions of spd_tools: one for LP4x and one for DDR4. This change is the first step in unifying these into a single tool. This change implements a unified version of the spd_gen tool, by combining the functionality currently in lp4x/gen_spd.go and ddr4/gen_spd.go. The unified version takes the memory technology as an argument, and generates SPD files for all platforms supporting that technology. BUG=b:191776301 TEST=Compare the SPDs generated by the old and new versions of the tool for all supported platforms. For reference, the test script used is here: https://review.coreboot.org/c/coreboot/+/57511 Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I7fc036996dbafbb54e075da0c3ac2ea0886a6db2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* amdfwtool: Detect the flag multilevel to decide the actual valueZheng Bao2021-09-171-10/+16
| | | | | | | | | | | | To save the space for FW, some of the FWs are going to be defined as LVL2 entries. To be compatible to "flattened" layout, we still drop the LVL2 entry to level1 if there is only one level. Change-Id: Ibe8cdd5c14225899352b02bb19aae6059d56d428 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* util/liveiso: Make neovim the default editorFelix Singer2021-09-162-4/+12
| | | | | | | | | | | | | Make neovim the default editor and create an alias for vim. The NixOS module for neovim is currently broken. Thus, add a note to `description.md` to switch to that later. Change-Id: I9345a6e32f3035565e55e50579c97121b4987d83 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57393 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/nixshell: Add Nix shell for toolchain compilationFelix Singer2021-09-161-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a Nix shell file which provides an environment for compilation of the coreboot toolchain. The Nix shell can be used by running the following command: $ nix-shell --pure util/nixshell/toolchain.nix The `--pure` parameter is optional, but it makes sure that the environment is as minimal as possible and does not contain any unrelated or unneeded software or configuration. Once compiled, the coreboot toolchain can be used without loading the shell environment. If `--pure` is used, SSL connections won't work since the `SSL_CERT_FILE` environment variable is not configured, which makes the build tool unable to download the source files. Thus, let it point to the system certificate store. Change-Id: I341ee28c5451d2c6cb4ff22de67161d99f4ca77a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* elogtool: add "add" commandRicardo Quesada2021-09-161-3/+181
| | | | | | | | | | | | | | | | | | | Adds "add" command to elogtool. This command allows adding elog events manually. It supports event type and, optionally, event data. If the free buffer space is < 1/4 of the total space, it shrinks the buffer, making sure that ~1/4 of the free space is available. BUG=b:172210863 TEST=./elogtool add 0x17 0101 ./elogtool add 0x18 Repeated the same tests on buffers that needed to be shrunk. Change-Id: Ia6fdf4f951565f842d1bff52173811b52f617f66 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* elogtool: add next_available_event_offset functionRicardo Quesada2021-09-161-22/+32
| | | | | | | | | | | | | | | | | | | This function is "extracted" from cmd_clear(). This new function will be called from cmd_add(), and new command that will be added in a future CL (see CL chain). Additional minor fixes: - calls usage() if no valid commands are passed. - Slightly improves usage() output. Needed for cmd_clear() BUG=b:172210863 TEST=elogtool clear Change-Id: I0d8ecc893675758d7f90845282a588d367b55567 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* util/sconfig: Update static.c to include boot/coreboot_tables.hTim Wawrzynczak2021-09-161-0/+1
| | | | | | | | | | | | | | | This allows the devicetree to directly access names defined in the coreboot tables API. BUG=b:194967458 BRANCH=dedede Change-Id: Ieb2d00095f54b2363a21f9c5ef8205110a36f746 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* amdfwtool: Add new SOC mendocinoZheng Bao2021-09-151-0/+6
| | | | | | | | Change-Id: I54492600dd954a5585ce3b1d842d264a4a50907a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* util/liveiso: Install UEFITool packagesFelix Singer2021-09-151-0/+2
| | | | | | | | | | | | | | | | | | | | | Install both versions of UEFITool, the one with the old engine and the new one. It's not possible to use both packages in the same environment, since there is a collision between the names of the binary files. To make sure a specific package is used, a new environment needs to be spawned with the following command: $ nix-shell -p <package_name> The UEFITool binaries can be executed from the shell then. Change-Id: Ia5d679c6e7cd01c2ab819bd6c085596a926c494d Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* util/kconfig: Add pre-built parserPatrick Georgi2021-09-134-0/+6465
| | | | | | | | | | | | | | | | | | | | | | | | | It avoids the dependency on bison/flex, minimally speeds up the build and also works around weird race conditions in some versions of bison that need more investigation. The issue this avoids manifests as a build error when creating parser.tab.c: input in flex scanner failed make: *** [util/kconfig/Makefile.inc:66: build/util/kconfig/parser.tab.c] Error 2 Since the error happens within bison the alternative would be to make bison part of our crossgcc environment to ensure that no broken OS build is used. BUG=b:197515860 TEST=things build with bison not installed Change-Id: Ib35dfb7beafc0a09dc333e962b1e3f33df46a854 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/kconfig: Simplify dependencies for parser.tab.*Patrick Georgi2021-09-131-4/+2
| | | | | | | | | | | | | | | | | | | | With parser.tab.h depending on parser.tab.c it's possible for make to initiate the creation of parser.tab.c, then try to compile it, even though parser.tab.h is still missing. This isn't normally an issue yet because bison creates them both at a time but with pre-compiled files this will become a problem. Pattern rules support (until recently as a special case that no other type of rule could implement) multiple targets that are actually treated as "one command creates multiple output files" so use that to state the relationship properly. Change-Id: I4aa7eca9d3123808e0665a15a99c04fac7384940 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/sconfig: Extract handling of SMBIOS dataAngel Pons2021-09-131-17/+26
| | | | | | | | | | | Move the code that handles devices' SMBIOS data into a helper function. Change-Id: I4f36d6c6f26e79558d360d319d09b0b8426def0e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57369 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/sconfig: Always generate SMBIOS CPP guardsAngel Pons2021-09-131-10/+4
| | | | | | | | | | | | | Manually maintaining a list of fields just to avoid printing some unnecessary CPP guards isn't worth the maintenance burden. Instead, always generate these guards, even if they guard nothing. Change-Id: I6c84180d83ac39a895e02d196acb7074eb052d7f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57459 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* elogtool: add "clear" commandRicardo Quesada2021-09-103-45/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds "clear" command to cbfsutil/elogtool tool. "clear" clears the RW_ELOG region by using either: * flashrom if no file is provided * or using file write if an input file is provided. The region is filled with ELOG_TYPE_EOL. And a ELOG_TYPE_LOG_CLEAR event is inserted. Additionally, it does a minor cleanup to command "list", like: * use buffer_end() * add "list" to the cmds struct * and make elog_read() very similar to elog_write() Usage: $ elogtool clear BUG=b:172210863 TEST=elogtool clear && elogtool list elogtool clear -f invalid.raw elogtool clear -f valid.raw Change-Id: Ia28a6eb34c82103ab078a0841b022e2e5e430585 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* util/liveiso/console.nix: Remove unneeded argument bodyFelix Singer2021-09-101-2/+0
| | | | | | | | Change-Id: Iebd994a46e870e42431d0fc71dd14b1c2b01f9aa Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57536 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/liveiso: Disable strict checking of access to MMIO memoryFelix Singer2021-09-101-1/+5
| | | | | | | | Change-Id: Ie859490d3cb3b8c56437cbd6c3e46525c580d3f4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57535 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/cbmem: Add -2/--2ndtolast option to print second-to-last boot logJulius Werner2021-09-091-11/+31
| | | | | | | | | | | | | | | | On some platforms, runtime firmware crashes write logs to the CBMEM console. For those, since a crash reboots the system, by the time we have a chance to run `cbmem` again the boot where the crash happened will be the one before the "last" (current) boot. So cbmem -1 doesn't show the interesting part, and cbmem -c potentially shows a lot that is cumbersome to dig through. This patch introduces a new option cbmem -2 to explicitly show only the boot cycle before the last one. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I6725698f4c9ae07011cbacf0928544cebb4ad6f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
* util/amdtools: Add script to update the SPI speed in the EFS headerMartin Roth2021-09-081-0/+121
| | | | | | | | | | | | | | | | | | | | The update_efs_spi_speed allows changing the SPI speed manually in a binary that has already been built. This will allow binaries not built for the EM100 SPI ROM emulator to be updated so that they will work. There is a corresponding change that will check to see if the EFS value has been modified from the original speed and will prevent coreboot from updating the SPI speed and mode. BUG=b:177233017 TEST=Update SPI speed in existing binary. See that SPI speed has changed. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I905a9fd8bd93a28aab927dffecbbcf24934b9e03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56644 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sconfig: Ensure at least one `device` node below each `chip`Nico Huber2021-09-083-147/+160
| | | | | | | | | | | | | | | | | | | | Even though `device` entries are children of `chip` entries in the devicetree source format, the chips in the translated C structures are only hooked up to device nodes. Hence, any chip with all its settings will be silently dropped by sconfig if there is no device node below it. Let's adapt the parser to ensure that there is at least one `device` entry. The intermediate `chipchildren_dev` rule applies until the first `device` entry is found, then everything continues as before with the `chipchildren` rule. Change-Id: I54830bc1fc7d00a0605f3fe4d36a83ef57ef3312 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51119 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* autoport: search for the HDA device on PCHIru Cai2021-09-062-27/+62
| | | | | | | | | | | Haswell has its Mini-HD device and is at card0, so we need to search for the PCH HD Audio device instead of using card0. Change-Id: I2bc420fdbe9731ae835f63add85db79f04201da4 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34357 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-06 03:03:18 +0000