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* util/elogtool: Add support for parsing CrOS diagnostics logHsuan Ting Chen2022-10-141-5/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the "_DEPRECATED_" tag from ChromeOS diagnostics event and add a subtype: "ELOG_CROS_DIAGNOSTICS_LOGS" under it. The data of "ELOG_CROS_DIAGNOSTICS_LOGS" (0x02) contains: * An uint8_t of subtype code * Any number of "ChromeOS diagnostics logs" events Each "ChromeOS diagnostics log" represents the result of one ChromeOS diagnostics test run. It is stored within an uint8_t raw[3]: * [23:19] = ELOG_CROS_DIAG_TYPE_* * [18:16] = ELOG_CROS_DIAG_RESULT_* * [15:0] = Running time in seconds Also add support for parsing this event. The parser will first calculate the number of runs it contains, and try to parse the result one by one. BUG=b:226551117 TEST=Build and boot google/tomato to OS, localhost ~ # elogtool list 0 | 2022-09-26 04:25:32 | Log area cleared | 186 1 | 2022-09-26 04:25:50 | System boot | 0 2 | 2022-09-26 04:25:50 | Firmware vboot info | boot_mode=Manual recovery | recovery_reason=0x2/0 (Recovery button pressed) | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown 3 | 2022-09-26 04:25:50 | EC Event | Keyboard Recovery 4 | 2022-09-26 04:26:01 | Memory Cache Update | Normal | Success 5 | 2022-09-26 04:26:06 | System boot | 0 6 | 2022-09-26 04:26:07 | Firmware vboot info | boot_mode=Diagnostic | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown 7 | 2022-09-26 04:26:07 | Diagnostics Mode | Diagnostics Logs | type=Memory check (quick), result=Aborted, time=0m0s | type=Memory check (full), result=Aborted, time=0m0s | type=Storage self-test (extended), result=Aborted, time=0m1s Change-Id: I02428cd21be2ed797eb7aab45f1ef1d782a9c047 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* util/cbfstool: Wrap logging macros in do - whileFred Reitberger2022-10-133-9/+9
| | | | | | | | | | | | | | | Wrap the console logging macros with do { ... } while (0) so they act more like functions. Add missing semicolons to calls of these macros. TEST=compile only Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I721a4a93636201fa2394ec62cbe4e743cd3ad9d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* util/superiotool/nuvoton.c: Add NCT6687D-W register definitionsMichał Żygowski2022-10-121-0/+181
| | | | | | | | | | | | | Based on public NCT6686D hardware datasheet revision 0.5 which should be similar to NCT6687D. TEST=Dump NCT6687D, GPIO and EC registers on MSI PRO Z690-A WIFI DDR4 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I38db1de0f3d3b6de14bcb758afc9804c072c1895 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
* util/amdfwread: Fix cookie error messageArthur Heymans2022-10-111-1/+1
| | | | | | | | | Change-Id: I580675fcbf8c5058ade371c6b9edb7b7070a78a3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* util/amdfwutil: Order enum and use hex consistentlyArthur Heymans2022-10-112-40/+38
| | | | | | | | | | | | | | | | | | | | | This makes it easier to match the code to the datasheet (55758, NDA only). This also removes the duplicate lines: "{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }," TESTED: google/vilboz still boots. Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
* util/amdfwtool: Add Mendocino to usageFred Reitberger2022-10-101-1/+1
| | | | | | | | | | | Add missing Mendocino soc to usage print. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I8b995fccc23dcca87d45cc13fbb1ebbc1f0e2add Reviewed-on: https://review.coreboot.org/c/coreboot/+/68226 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool: Add preliminary code for morgana & glinda SOCsMartin Roth2022-10-101-1/+11
| | | | | | | | | | | | | This allows amdfwtool to recognize the names for the upcoming morgana and glinda SoCs. It does not yet do anything for those SoCs, but this allows the morgana SoC to build. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I766ce4a5863c55cbc4bef074ac5219b498c48c7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68193 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/lint/lint-stable-003-whitespace: Fix shell variable nameFred Reitberger2022-10-101-1/+1
| | | | | | | | | | | | | Fix shell variable "LINTDIR" so that helper_functions.sh can be found. TEST=`./util/lint/lint lint-stable --junit` no longer prints "cannot open /helper_functions.sh: No such file" Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I68f2e65fa1c9297ad6b58b77576deaeef8bd76e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* util/inteltool: Add support for (non-ULT) BroadwellAngel Pons2022-10-084-0/+14
| | | | | | | | | | Add support for traditional (non-ULT) Broadwell. Change-Id: Ibe0ed9badd580e28060fe8df14a01352d4c1e11e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* util/inteltool: Add 9 series PCH supportAngel Pons2022-10-087-0/+41
| | | | | | | | | | Add the PCI device IDs for 9 series PCHs. Change-Id: Id216cd071b09c93ee6a4792944c6fad39254aa3b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* util/coreboot-configurator: Update the READMESean Rhodes2022-10-071-5/+6
| | | | | | | | | | | | Update the README with new instructions for Debian 11 and MX Linux. Also add the build dependencies. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6942b9532e8d82f7fc5d6455c96913bcba6e983e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* util/inteltool: Add support for Alderlake P in inteltoolKacper Stojek2022-10-076-1/+644
| | | | | | | | | | | | TEST=Dump registers on Clevo NS70PU with Intel® Core™ i7-1260P Document number: 626817, 630094, 655258 Change-Id: I2ba4ef7eee33d4dd762a05dd755de5e4d2e566dd Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66825 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool: Generate hashes for signed AMDFW componentsKangheui Won2022-10-024-8/+233
| | | | | | | | | | | | | | | | Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage can pass it to PSP. The PSP will use these hashes to verify the integrity of those signed firmwares. BUG=b:203597980 TEST=Build Skyrim BIOS image. Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool: Add options to separate signed firmwaresKangheui Won2022-10-022-13/+299
| | | | | | | | | | | | | | | | | | Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool: Include the header with __packed definitionKarthikeyan Ramasubramanian2022-10-023-0/+4
| | | | | | | | | | | | | | | | Checkpatch script recommends to use __packed instead of __attribute__((packed)). Currently the build rule for amdfwtool does not include the required header file with __packed definition. Update the compiler flag to include the required header file. BUG=None TEST=Build amdfwtool. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I448cbad533608dd5c2bd4f2d827fcc5db5dee5cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/67384 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/docker/coreboot-sdk: add graphicsmagick-imagemagick-compatTom Hiller2022-10-021-0/+1
| | | | | | | | | | | | edkII requires ImageMagick's `convert` to compile. The `graphicsmagick-imagemagick-compat` package provides `convert` without the full ImageMagick library. Change-Id: I8fc01526842eb408b0015c0652043c20f826a015 Signed-off-by: Tom Hiller <thrilleratplay@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* util/lint: Update tools that use git to use a libraryMartin Roth2022-09-3023-152/+273
| | | | | | | | | | | | | | | | | Each of the tools that used git had similar functionality. This combines all of that into a single script that gets sourced by each. This makes maintenance much easier. By doing this and updating each of the scripts to do the correct thing if the script isn't being run in a git repository, it makes them work much better for the releases, which are just released as a tarball, without any attached git repository. Change-Id: I61ba1cc4f7205e0d4baf993588bbc774120405cb Signed-off-by: Martin Roth <martin@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* util/lint: Update spelling.txt, add makefile to sort itMartin Roth2022-09-302-37/+189
| | | | | | | | | | | | | | | | | | | - Update spelling.txt with Lintian changes - Remove words that are going to mess up code - Add comments to the header about what words should be removed, along with where the files - Add Makefile to sort the list Note that this undoes some of the sorting that Patrick introduced in commit CB:38632 - ID: 805b291830 I just cannot reproduce his sort order, even using the script he put into the commit message. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic131d5b08409f43eb700dcc8f125af00cff53d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64893 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool/data_parse: fix PMU subprogram/instance ID handlingFelix Held2022-09-301-4/+4
| | | | | | | | | | | | | | | | The parsing of the PMU binary subprogram and instance numbers only worked correctly for the cases where the ID in the name in the fw.cfg file was between 0 and 9, but returned wrong results if it was between a and f. Switch to using strtol with a base of 16 instead of subtracting the char '0' from the char in the filename in find_register_fw_filename_bios_dir to fix this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic5fd41daf9f26d11c1f86375387c1d7beac04124 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* util/spd_tools: Change Mendocino to use 0x13 for LP5x memory typeRobert Zieba2022-09-291-1/+3
| | | | | | | | | | | | | | | | | Mendocino supports LP5x but currently doesn't support SPDs that use the LP5x memory type, 0x15. This commit updates set 1 SPDs, which are currently only used for mendocino, to use 0x13 for their memory type. BUG=b:245509394 TEST=Generated SPDs, verified that only set 1 have changed to 0x13 Change-Id: I46606cb5ff871296d0214e1f781c3b22e93d24ea Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67747 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* intelmetool: Add PCI ID for Bay TrailDenis 'GNUtoo' Carikli2022-09-281-0/+2
| | | | | | | | | | Tested on a Dell Venue 8 Pro tablet Change-Id: Ic8f162ea82b910082af4b4e05fa1408fd24f2c88 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/amdfwtool: Add support for PSP NVRAM base addr and sizeRitul Guru2022-09-222-29/+75
| | | | | | | | | | | | Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/coreboot-configurator: Update legacy_8254_timer descriptionSean Rhodes2022-09-221-2/+2
| | | | | | | | | | | The help text and label for legacy_8254_timer is inverted, so update this so that it is correct. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I866a15886d1cfd2b77094742787dee7a36a54e85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65348 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/coreboot-configurator: Add RPM spec fileSean Rhodes2022-09-222-0/+96
| | | | | | | | | | | Add RPM spec to allow building RPMs, for both coreboot-configurator and nvramtool, for Fedora. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I80a77d0f2246409c06e22abb229d63c4611a9fb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65346 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/coreboot-configurator: Update Debian dependanciesSean Rhodes2022-09-221-1/+1
| | | | | | | | | | | Change the control file to allow either libyaml-cpp0.6 or libyaml-cpp0.7. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I754d3e2018ab78fcb657d313c8662313738b190a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* tests: Add support for tests build failures detectionJakub Czapiga2022-09-211-3/+4
| | | | | | | | | | | | This patch introduces new target: junit.xml-unit-tests, which builds and runs unit-tests. It also creates build log containing build logs. This feature allows for one to see build failures in Jenkins dashboard. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I94184379dcc2ac10f1a47f4a9d205cacbeb640fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/67372 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* crossgcc: Upgrade llvm from version 14.0.6 to 15.0.0Elyes Haouas2022-09-1810-7/+11
| | | | | | | | | | Test build for QEMU x86 i440fx/piix4. Change-Id: I3144a83fcbd92eec51d70e9be33ff2fcb2821731 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67416 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* crossgcc: Upgrade cmake from 3.23.2 to 3.24.2Elyes Haouas2022-09-183-2/+2
| | | | | | | | Change-Id: I81a8371190513ca34d3c5efb0e3770ac3d873b03 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* cbmem: use aligned_memcpy for reading lb_cbmem_entry informationYidi Lin2022-09-181-14/+14
| | | | | | | | | | | | | | | | The lbtable contains the memory entries that have fields unnaturally aligned in memory. Therefore, we need to perform an aligned_memcpy() to fix the issues with platforms that don't allow unaligned accesses. BUG=b:246887035 TEST=cbmem -l; cbmem -r ${CBMEM ID} Change-Id: Id94e3d65118083a081fc060a6938836f6176ab54 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* riscv: Enable the newfangled way of selecting instruction setsPatrick Georgi2022-09-172-1/+11
| | | | | | | | | | | | | | | | | | | gcc12+ will require riscv architecture selection to come not only with featurei suffixd charactersa, it also comes with feature_ful suffix_ed words_mith. Much creative, very appreciate. To accommodate for this madness, enable the already existing (but off by default) support for that in our gcc11 build, support using by detecting the compiler's behavior in xcompile and pass that knowledge along to our build system. Then cross our fingers and hope for the best! Change-Id: I5dfeed766626e78d4f8378d9d857b7a4d61510fd Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* util/kconfig/regex.c: Remove leftoverElyes Haouas2022-09-161-5/+0
| | | | | | | | | | coreboot doesn't support the MIPS architecture anymore. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I404d034949a7786d7971117081537baf27ff2e22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* crossgcc [binutils]: Remove 'enable-plugins' optionElyes Haouas2022-09-161-2/+2
| | | | | | | | | | | unneeded 'enable-plugins' option sneaked in..., so remove it. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id1d7f2c7e6b70c28e1060c6ee915363ffe412ef6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* crossgcc [binutils]: Remove invalid enable-interwork optionElyes Haouas2022-09-161-2/+1
| | | | | | | | | | | | 'enable-interwork' is not a binutils configure option. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I29cd6137c700ff6871868a723daf33909aa218ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/65609 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* sconfig: Allow to specify device operationsNico Huber2022-09-157-344/+413
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we only have runtime mechanisms to assign device operations to a node in our devicetree (with one exception: the root device). The most common method is to map PCI IDs to the device operations with a `struct pci_driver`. Another accustomed way is to let a chip driver assign them. For very common drivers, e.g. those in soc/intel/common/blocks/, the PCI ID lists grew very large and are incredibly error-prone. Often, IDs are missing and sometimes IDs are added almost mechanically without checking the code for compatibility. Maintaining these lists in a central place also reduces flexibility. Now, for onboard devices it is actually unnecessary to assign the device operations at runtime. We already know exactly what operations should be assigned. And since we are using chipset devicetrees, we have a perfect place to put that information. This patch adds a simple mechanism to `sconfig`. It allows us to speci- fy operations per device, e.g. device pci 00.0 alias system_agent on ops system_agent_ops end The operations are given as a C identifier. In this example, we simply assume that a global `struct device_operations system_agent_ops` exists. Change-Id: I2833d2f2450fde3206c33393f58b86fd4280b566 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* util/ifittool: Error out if microcodes do not fit the FIT tableJeremy Compostella2022-09-151-11/+8
| | | | | | | | | | | | | | | | | | | | | | | | parse_microcode_blob() returns success when it reaches max_fit_entries microcode. It makes the FIT table size verification in fit_add_microcode_file() useless. This patch makes parse_microcode_blob() error out if max_fit_entries is reached. Note that this size verification is critical as a FIT table only partially listing the microcode patches can lead to boot failures as recently observed on Raptor Lake-P. BRANCH=firmware-brya-14505.B BUG=b:245380705 TEST=compilation errors out when trying to stitch more than CONFIG_CPU_INTEL_NUM_FIT_ENTRIES microcode patches. Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Id9c5fb6c1e264f3f5137d29201b9021c72d78fde Reviewed-on: https://review.coreboot.org/c/coreboot/+/67454 Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
* util/lint: Add a check for touchpads using the "probed" flagMatt DeVillier2022-09-141-0/+29
| | | | | | | | | | | | | | | | | As of commit 2cf52d80a6ec ("mb/*/{device,override}tree: Set touchpads to use detect (vs probed) flag") all touchpads in the tree have been switched from using the 'probed' flag to 'detect.' Add a lint check to ensure no touchpads are added with the probed flag. TEST=manually change one touchpad to use 'probed' flag and ensure lint check catches it. Change-Id: Ie0aee2e3778fc56c6c21c97995738a147a1fa0d4 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67486 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* crossgcc: binutils: Remove invalid enable-multilibs optionElyes Haouas2022-09-141-1/+1
| | | | | | | | | | | | | | Looks like somewhere after the original implementation it was renamed to --enable-multilib without the s. 'enable-multilibs' is not a valid option for binutils. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I105cc9fa489aed24905dedb785c70bc69ed18970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65608 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* intelp2m: Add Go Managing Dependencies System supportMaxim Polyakov2022-09-1218-43/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add go.mod containing the full name of the project according to the docs [1]: review.coreboot.org/coreboot.git/util/intelp2m, and also, based on this, rename the internal packages to point to the absolute path. This will allow Go Managing Dependencies System to integrate packages from intelp2m to third-party Go written on the Go language [1]. This also requires fixing the Golang compiler version in go.mod: use go1.18 [2], the latest up-to-date version. [1] https://web.archive.org/web/20220910100342/https://go.dev/doc/modules/managing-dependencies [2] https://web.archive.org/web/20220910100206/https://tip.golang.org/doc/go1.18 [ TEST ] 1) Import the coreboot project into some go project: $cd path/to/go-project $go get review.coreboot.org/coreboot.git go: downloading review.coreboot.org/coreboot.git v0.0.0-20220903004133 -39914a50ae16 go: added review.coreboot.org/coreboot.git v0.0.0-20220903004133 -39914a50ae16 Thus, 'go get' correctly downloaded the contents of the repository. 2) Import intelp2m: $cd path/to/go-project $go get review.coreboot.org/coreboot.git/util/intelp2m review.coreboot.org/coreboot.git/util/intelp2m imports ./config: "./config" is relative, but relative import paths are not supported in module mode review.coreboot.org/coreboot.git/util/intelp2m imports ./parser: "./parser" is relative, but relative import paths are not supported in module mode Thus, the problem is in the package names, but after this patch, the import should be without errors. 3) Import a repository with an incorrect url: $cd path/to/go-project $go get review.coreboot.org/coreboot/test go: unrecognized import path "review.coreboot.org/coreboot/test": reading https://review.coreboot.org/coreboot/test?go-get=1: 404 Not Found This has not happened in previous cases. Change-Id: I12efae31227129b8c884af10fb233f398c4094e7 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* util/ifittool: Fix buffer overflow with padded microcode patchesJeremy Compostella2022-09-121-1/+2
| | | | | | | | | | | | | | | | | | Some microcode patches are padded with zeros, which make parse_microcode_blob() read beyond the end of the buffer. BRANCH=firmware-brya-14505.B BUG=b:245380705 TEST=No segmentation fault with a padded microcode patch Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Id9c5fb6c1e264f3f5137d29201b9021c72d78fdd Reviewed-on: https://review.coreboot.org/c/coreboot/+/67460 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/lint/lint: Add -I option to invert test resultsMartin Roth2022-09-071-2/+10
| | | | | | | | | | | | | | To test the linters, we want to invert the results so that any test that passes shows up as a failure. This will allow us to verify that all of the linters are working correctly. This will be tested nightly as well as on changes to the lint tools. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia8024c6ab0c91fd9f630f37dc802ed3bc6b4608c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/spd_tools: Update LP5X support for ADL/RPL/MTLCaveh Jalali2022-09-071-13/+4
| | | | | | | | | | | | | | | | | | | | | | | This updates the SPD utility and generated SPDs for LP5X to use memory type code 0x15 (LPDDR5X) instead of 0x13 (LPDDR5). This is done based on Intel Tech Advisory Doc ID #616599 dated May 2022, page 15. SPDs were regenerated with: "util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5" This only affects the SPDs for 2 memory parts for Intel SoCs and the only board referencing these is rex. BUG=b:242765117 TEST=inspected SPD hex dump Change-Id: Iadb4688f1cb4265dab1dc7c242f0c301d5498b83 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* lint/checkpatch: Fix incorrect camelcase detection on numeric constantElyes Haouas2022-09-061-1/+1
| | | | | | | | | | This reduce the difference with linux v6.0-rc3. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I15e1a935665c38b8a2109d412b1d16f935cbb402 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* util/lint/lint-stable-019-header-files: add testMartin Roth2022-09-061-0/+22
| | | | | | | | | | Add a test to make sure that the linter fails correctly. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I971951d4248dd10abe4c622025fdaf86e014c6cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/67351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* util/lint: Add rules.h & compiler.h to 019-header-files linterMartin Roth2022-09-061-2/+1
| | | | | | | | | | | The rules.h & compiler.h includes were removed in previous commits, so add the checks to keep them out to the linter. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If4964ff26f5e83abbbdd26c2b1cd9a2eab5a0a0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* util/lint: ignore util/goswid, a new submoduleMartin Roth2022-09-051-1/+1
| | | | | | | | | | | git submodules should be ignored when parsing the coreboot tree for lint errors. Those should be handled in their own commit checks. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I62b58f0c536312fe4677855bca8f44bc7d3ebc85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* util/amdfwtool/amdfwread: Fix incorrect option indexKarthikeyan Ramasubramanian2022-09-041-6/+5
| | | | | | | | | | | | | | | | | | | index I/O argument to getopt_long is not the index to argv. Instead it is an index into the optlong array corresponding to the parsed option. Also getopt() uses a global variable optind to track the index of the next argument to be processed. Use the optindex variable as an index to extract the filename from argv. BUG=None TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush BIOS image. Observed no changes before and after the changes. Change-Id: I33c74a0c8e12c5af76954524cf7294b7541d286b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66553 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/spd_tools: Rebuild utils when source changesCaveh Jalali2022-09-041-4/+4
| | | | | | | | | | | | | | | | | This adds source file dependencies to utilities so that they are rebuilt when the source is changed. Previously, binaries were only built if they did not already exist and never rebuilt to reflect source file changes. BUG=none TEST=verified binaries are rebuilt when source files are touched. Change-Id: I4775fe0e00e0f5d4f8b4b47331d836aba53c0e69 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* util/lint: Add lint tests to make sure they fail correctlyMartin Roth2022-09-041-34/+143
| | | | | | | | Change-Id: I1ff3302acdd5bc5d17a5d394d953b6877750b6a6 Signed-off-by: Martin Roth <martin@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/lint/lint: Reformat usageMartin Roth2022-09-031-1/+10
| | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I684d374bd02a42e178383c26936e137e173f8f7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* util/lint/lint: Add command line parsingMartin Roth2022-09-031-6/+31
| | | | | | | | | | | | | The lint script just did very basic argument parsing and required the sub-command and --junit argument to be in specific locations. I'm adding additional commands, so the first step is to add true command line parsing. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I7118c29e6c5d785b35a7ae12cf5984c43ebc3ab9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67191 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-01 05:44:36 +0000