From 01f4f5db9411c01de3e2814aea4b58bfe8dd76e3 Mon Sep 17 00:00:00 2001 From: Kilari Raasi Date: Wed, 16 Aug 2023 16:34:40 +0530 Subject: vc/intel/fsp/mtl: Add PsysPmax FspmUpd This patch adds the PsysPmax Upd to FSPM header file. FSPM: 1. Add 'PsysPmax' UPD 2. Address offset changes BUG=b:295126631 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I892b8c2d75e58a42d3f85006237827da01426ea7 Signed-off-by: Kilari Raasi Reviewed-on: https://review.coreboot.org/c/coreboot/+/77244 Reviewed-by: Ronak Kanabar Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Jakub Czapiga Reviewed-by: Eric Lai --- .../intel/fsp/fsp2_0/meteorlake/FspmUpd.h | 102 +++++++++++---------- 1 file changed, 56 insertions(+), 46 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h index 52677b096c87..b69bebab40e7 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h @@ -1416,7 +1416,17 @@ typedef struct { /** Offset 0x0585 - Reserved **/ - UINT8 Reserved32[273]; + UINT8 Reserved32[145]; + +/** Offset 0x0616 - Platform Power Pmax + PSYS PMax power, defined in 1/8 Watt increments. 0 - Auto Specified in 1/8 + Watt increments. Range 0-1024 Watts(0-8191). Value of 800 = 100W +**/ + UINT16 PsysPmax; + +/** Offset 0x0618 - Reserved +**/ + UINT8 Reserved33[126]; /** Offset 0x0696 - Thermal Design Current enable/disable Thermal Design Current enable/disable; 0: Disable; 1: Enable. [0] for IA, @@ -1433,7 +1443,7 @@ typedef struct { /** Offset 0x06B4 - Reserved **/ - UINT8 Reserved33[166]; + UINT8 Reserved34[166]; /** Offset 0x075A - VR Fast Vmode ICC Limit support Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds @@ -1459,7 +1469,7 @@ typedef struct { /** Offset 0x0772 - Reserved **/ - UINT8 Reserved34[146]; + UINT8 Reserved35[146]; /** Offset 0x0804 - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable @@ -1481,7 +1491,7 @@ typedef struct { /** Offset 0x0807 - Reserved **/ - UINT8 Reserved35; + UINT8 Reserved36; /** Offset 0x0808 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -1495,7 +1505,7 @@ typedef struct { /** Offset 0x0810 - Reserved **/ - UINT8 Reserved36[8]; + UINT8 Reserved37[8]; /** Offset 0x0818 - TxtDprMemoryBase Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable @@ -1550,7 +1560,7 @@ typedef struct { /** Offset 0x0849 - Reserved **/ - UINT8 Reserved37[32]; + UINT8 Reserved38[32]; /** Offset 0x0869 - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value. @@ -1737,7 +1747,7 @@ typedef struct { /** Offset 0x0A85 - Reserved **/ - UINT8 Reserved38; + UINT8 Reserved39; /** Offset 0x0A86 - SMBUS Base Address SMBUS Base Address (IO space). @@ -1757,7 +1767,7 @@ typedef struct { /** Offset 0x0A99 - Reserved **/ - UINT8 Reserved39[16]; + UINT8 Reserved40[16]; /** Offset 0x0AA9 - SOC/IOE ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc @@ -1766,7 +1776,7 @@ typedef struct { /** Offset 0x0AB9 - Reserved **/ - UINT8 Reserved40[55]; + UINT8 Reserved41[55]; /** Offset 0x0AF0 - Enable PCH PCIE RP Mask Enable/disable PCH PCIE Root Ports. 0: disable, 1: enable. One bit for each port, @@ -1818,7 +1828,7 @@ typedef struct { /** Offset 0x0AFE - Reserved **/ - UINT8 Reserved41[2]; + UINT8 Reserved42[2]; /** Offset 0x0B00 - DMIC ClkA Pin Muxing (N - DMIC number) Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_* @@ -1838,7 +1848,7 @@ typedef struct { /** Offset 0x0B11 - Reserved **/ - UINT8 Reserved42[3]; + UINT8 Reserved43[3]; /** Offset 0x0B14 - DMIC Data Pin Muxing Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_* @@ -1863,7 +1873,7 @@ typedef struct { /** Offset 0x0B27 - Reserved **/ - UINT8 Reserved43; + UINT8 Reserved44; /** Offset 0x0B28 - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T @@ -1879,7 +1889,7 @@ typedef struct { /** Offset 0x0B2A - Reserved **/ - UINT8 Reserved44[6]; + UINT8 Reserved45[6]; /** Offset 0x0B30 - CNVi DDR RFI Mitigation Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE @@ -1889,7 +1899,7 @@ typedef struct { /** Offset 0x0B31 - Reserved **/ - UINT8 Reserved45[11]; + UINT8 Reserved46[11]; /** Offset 0x0B3C - Debug Interfaces Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, @@ -1911,7 +1921,7 @@ typedef struct { /** Offset 0x0B3F - Reserved **/ - UINT8 Reserved46; + UINT8 Reserved47; /** Offset 0x0B40 - Serial Io Uart Debug BaudRate Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, @@ -1939,7 +1949,7 @@ typedef struct { /** Offset 0x0B47 - Reserved **/ - UINT8 Reserved47; + UINT8 Reserved48; /** Offset 0x0B48 - Serial Io Uart Debug Mmio Base Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode @@ -1955,7 +1965,7 @@ typedef struct { /** Offset 0x0B4D - Reserved **/ - UINT8 Reserved48; + UINT8 Reserved49; /** Offset 0x0B4E - Ring PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-15 @@ -1969,7 +1979,7 @@ typedef struct { /** Offset 0x0B50 - Reserved **/ - UINT8 Reserved49; + UINT8 Reserved50; /** Offset 0x0B51 - Memory Controller PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-15 @@ -2087,7 +2097,7 @@ typedef struct { /** Offset 0x0B64 - Reserved **/ - UINT8 Reserved50; + UINT8 Reserved51; /** Offset 0x0B65 - Write Timing Centering 1D Enables/Disable Write Timing Centering 1D @@ -2115,7 +2125,7 @@ typedef struct { /** Offset 0x0B69 - Reserved **/ - UINT8 Reserved51[10]; + UINT8 Reserved52[10]; /** Offset 0x0B73 - Read Equalization Training Enables/Disable Read Equalization Training @@ -2125,7 +2135,7 @@ typedef struct { /** Offset 0x0B74 - Reserved **/ - UINT8 Reserved52[2]; + UINT8 Reserved53[2]; /** Offset 0x0B76 - Write Timing Centering 2D Enables/Disable Write Timing Centering 2D @@ -2153,7 +2163,7 @@ typedef struct { /** Offset 0x0B7A - Reserved **/ - UINT8 Reserved53; + UINT8 Reserved54; /** Offset 0x0B7B - Command Voltage Centering Enables/Disable Command Voltage Centering @@ -2181,7 +2191,7 @@ typedef struct { /** Offset 0x0B7F - Reserved **/ - UINT8 Reserved54; + UINT8 Reserved55; /** Offset 0x0B80 - DIMM SPD Alias Test Enables/Disable DIMM SPD Alias Test @@ -2233,7 +2243,7 @@ typedef struct { /** Offset 0x0B88 - Reserved **/ - UINT8 Reserved55[2]; + UINT8 Reserved56[2]; /** Offset 0x0B8A - DIMM CA ODT Training Enable/Disable DIMM CA ODT Training @@ -2243,7 +2253,7 @@ typedef struct { /** Offset 0x0B8B - Reserved **/ - UINT8 Reserved56[3]; + UINT8 Reserved57[3]; /** Offset 0x0B8E - Read Vref Decap Training Enable/Disable Read Vref Decap Training @@ -2265,7 +2275,7 @@ typedef struct { /** Offset 0x0B91 - Reserved **/ - UINT8 Reserved57[4]; + UINT8 Reserved58[4]; /** Offset 0x0B95 - Duty Cycle Correction Training Enable/Disable Duty Cycle Correction Training @@ -2275,7 +2285,7 @@ typedef struct { /** Offset 0x0B96 - Reserved **/ - UINT8 Reserved58[17]; + UINT8 Reserved59[17]; /** Offset 0x0BA7 - ECC Support Enables/Disable ECC Support @@ -2309,7 +2319,7 @@ typedef struct { /** Offset 0x0BB3 - Reserved **/ - UINT8 Reserved59; + UINT8 Reserved60; /** Offset 0x0BB4 - IbeccProtectedRegionBases IBECC Protected Region Bases per IBECC instance @@ -2401,7 +2411,7 @@ typedef struct { /** Offset 0x0BF0 - Reserved **/ - UINT8 Reserved60[4]; + UINT8 Reserved61[4]; /** Offset 0x0BF4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP @@ -2660,7 +2670,7 @@ typedef struct { /** Offset 0x0C2B - Reserved **/ - UINT8 Reserved61[2]; + UINT8 Reserved62[2]; /** Offset 0x0C2D - Rapl Power Floor Ch0 Power budget ,range[255;0],(0= 5.3W Def) @@ -2711,7 +2721,7 @@ typedef struct { /** Offset 0x0C35 - Reserved **/ - UINT8 Reserved62; + UINT8 Reserved63; /** Offset 0x0C36 - Power Down Mode This option controls command bus tristating during idle periods @@ -2748,7 +2758,7 @@ typedef struct { /** Offset 0x0C3B - Reserved **/ - UINT8 Reserved63[8]; + UINT8 Reserved64[8]; /** Offset 0x0C43 - Ask MRC to clear memory content Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. @@ -2763,7 +2773,7 @@ typedef struct { /** Offset 0x0C45 - Reserved **/ - UINT8 Reserved64; + UINT8 Reserved65; /** Offset 0x0C46 - Post Code Output Port This option configures Post Code Output Port @@ -2783,7 +2793,7 @@ typedef struct { /** Offset 0x0C4A - Reserved **/ - UINT8 Reserved65[2]; + UINT8 Reserved66[2]; /** Offset 0x0C4C - BCLK RFI Frequency Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No @@ -2826,7 +2836,7 @@ typedef struct { /** Offset 0x0C62 - Reserved **/ - UINT8 Reserved66[11]; + UINT8 Reserved67[11]; /** Offset 0x0C6D - RH pTRR LFSR1 Mask Row Hammer pTRR LFSR1 Mask, 1/2^(value) @@ -2835,7 +2845,7 @@ typedef struct { /** Offset 0x0C6E - Reserved **/ - UINT8 Reserved67; + UINT8 Reserved68; /** Offset 0x0C6F - Command Pins Mapping BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller @@ -2851,7 +2861,7 @@ typedef struct { /** Offset 0x0C71 - Reserved **/ - UINT8 Reserved68[24]; + UINT8 Reserved69[24]; /** Offset 0x0C89 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -2887,7 +2897,7 @@ typedef struct { /** Offset 0x0C8E - Reserved **/ - UINT8 Reserved69[2]; + UINT8 Reserved70[2]; /** Offset 0x0C90 - PMR Size Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot @@ -2901,7 +2911,7 @@ typedef struct { /** Offset 0x0C95 - Reserved **/ - UINT8 Reserved70[143]; + UINT8 Reserved71[143]; /** Offset 0x0D24 - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable @@ -2917,7 +2927,7 @@ typedef struct { /** Offset 0x0D28 - Reserved **/ - UINT8 Reserved71[28]; + UINT8 Reserved72[28]; /** Offset 0x0D44 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. @@ -2933,7 +2943,7 @@ typedef struct { /** Offset 0x0D46 - Reserved **/ - UINT8 Reserved72[2]; + UINT8 Reserved73[2]; /** Offset 0x0D48 - SMBUS SPD Write Disable Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write @@ -2944,7 +2954,7 @@ typedef struct { /** Offset 0x0D49 - Reserved **/ - UINT8 Reserved73[34]; + UINT8 Reserved74[34]; /** Offset 0x0D6B - HECI Timeouts 0: Disable, 1: Enable (Default) timeout check for HECI @@ -2997,7 +3007,7 @@ typedef struct { /** Offset 0x0D73 - Reserved **/ - UINT8 Reserved74[100]; + UINT8 Reserved75[100]; /** Offset 0x0DD7 - Avx2 Voltage Guardband Scaling Factor AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in @@ -3020,7 +3030,7 @@ typedef struct { /** Offset 0x0DDA - Reserved **/ - UINT8 Reserved75[2]; + UINT8 Reserved76[2]; /** Offset 0x0DDC - SerialIoUartDebugRxPinMux - FSPM Select RX pin muxing for SerialIo UART used for debug @@ -3046,7 +3056,7 @@ typedef struct { /** Offset 0x0DEC - Reserved **/ - UINT8 Reserved76[164]; + UINT8 Reserved77[164]; /** Offset 0x0E90 - TME Exclude Base Address TME Exclude Base Address. @@ -3066,7 +3076,7 @@ typedef struct { /** Offset 0x0EA1 - Reserved **/ - UINT8 Reserved77[7]; + UINT8 Reserved78[7]; } FSP_M_CONFIG; /** Fsp M UPD Configuration -- cgit v1.2.3