From 0f76a18c3a70fbdb1505a7e23b554026596be5c2 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Thu, 13 Jan 2022 09:09:05 -0800 Subject: soc/intel/denverton_ns: Add the Primary to Sideband Bridge definition This change adds the Primary to Sideband Bridge(B0, D31, F1) definition for the platform in order to maintain the common block API build. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao Change-Id: I1c4ddfce6cc6e41b2c63f99990d105b4bbb6f175 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61074 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Subrata Banik --- src/soc/intel/denverton_ns/include/soc/pci_devs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index 9fa38e40e4a7..f1e120c339c5 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -143,6 +143,7 @@ #define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) +#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) #define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) /* VT-d support value to match FSP settings */ -- cgit v1.2.3