From 15d55439dabafd8d4d874b818234d3859fda7d4c Mon Sep 17 00:00:00 2001 From: Varshit Pandya Date: Thu, 22 Feb 2024 20:37:17 +0530 Subject: soc/amd/glinda: Update GPP_CLK_OUTPUT_AVAILABLE to 7 Glinda started as a copy of mendocino and GPP_CLK_OUTPUT_AVAILABLE was not updated. GPP_CLK_OUTPUT_AVAILABLE should be 7 as per Processor Programming Reference (PPR) (#57254), table "GPP ClkREQB Mapping". Change-Id: I26e9dea58b2ddf5cbedbcccb8bcbc5f9efab3165 Signed-off-by: Varshit Pandya Reviewed-on: https://review.coreboot.org/c/coreboot/+/80701 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/soc/amd/glinda/include/soc/southbridge.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/glinda/include/soc/southbridge.h b/src/soc/amd/glinda/include/soc/southbridge.h index 9cd835b21a60..b7ac8a8509da 100644 --- a/src/soc/amd/glinda/include/soc/southbridge.h +++ b/src/soc/amd/glinda/include/soc/southbridge.h @@ -87,7 +87,7 @@ #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ /* FCH MISC Registers 0xfed80e00 */ -#define GPP_CLK_OUTPUT_AVAILABLE 4 +#define GPP_CLK_OUTPUT_AVAILABLE 7 #define MISC_CLKGATEDCNTL 0x2c #define ALINKCLK_GATEOFFEN BIT(16) -- cgit v1.2.3