From 1952d13a414229f1867a8a9c00fc07df07d7042c Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 16 Nov 2023 00:54:30 +0100 Subject: nb/amd/pi/00730F01: restructure chip ops Since this chip is a SoC and also to bring the chipset devicetree more in line with the chipset devicetree of Sandy Bridge, merge the chip operations of the northbridge's root complex and the northbridge itself into one chip operations structure and use it at the top level of the devicetree. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held Change-Id: I8b42bac07b1409bbc797bc4428cf9f84a40e94c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79084 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- .../pcengines/apu2/variants/apu2/devicetree.cb | 16 ++++++------- .../pcengines/apu2/variants/apu3/devicetree.cb | 16 ++++++------- .../pcengines/apu2/variants/apu4/devicetree.cb | 16 ++++++------- .../pcengines/apu2/variants/apu5/devicetree.cb | 16 ++++++------- src/northbridge/amd/pi/00730F01/chipset.cb | 26 ++++++++++------------ src/northbridge/amd/pi/00730F01/northbridge.c | 9 ++------ 6 files changed, 42 insertions(+), 57 deletions(-) diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index 4a09ce7eec87..7725c659c6d9 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -1,16 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -chip northbridge/amd/pi/00730F01/root_complex +chip northbridge/amd/pi/00730F01 device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 - device ref iommu on end - device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) - device ref gpp_bridge_1 on end # LAN3 - device ref gpp_bridge_2 on end # LAN2 - device ref gpp_bridge_3 on end # LAN1 - device ref gpp_bridge_4 on end # mPCIe slot 1 - end + device ref iommu on end + device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) + device ref gpp_bridge_1 on end # LAN3 + device ref gpp_bridge_2 on end # LAN2 + device ref gpp_bridge_3 on end # LAN1 + device ref gpp_bridge_4 on end # mPCIe slot 1 chip southbridge/amd/pi/hudson device ref xhci on end # XHCI HC0 muxed with EHCI 2 diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index dcff5abb71e9..5c169208b9cf 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -1,16 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -chip northbridge/amd/pi/00730F01/root_complex +chip northbridge/amd/pi/00730F01 device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 - device ref iommu on end - device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) - device ref gpp_bridge_1 on end # LAN3 - device ref gpp_bridge_2 on end # LAN2 - device ref gpp_bridge_3 on end # LAN1 - device ref gpp_bridge_4 on end # mPCIe slot 1 - end + device ref iommu on end + device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) + device ref gpp_bridge_1 on end # LAN3 + device ref gpp_bridge_2 on end # LAN2 + device ref gpp_bridge_3 on end # LAN1 + device ref gpp_bridge_4 on end # mPCIe slot 1 chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus device ref xhci on end # XHCI HC0 muxed with EHCI 2 diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index 02390d2d8984..57eebb65220f 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -1,16 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -chip northbridge/amd/pi/00730F01/root_complex +chip northbridge/amd/pi/00730F01 device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 - device ref iommu on end - device ref gpp_bridge_0 on end # LAN1 - device ref gpp_bridge_1 on end # LAN2 - device ref gpp_bridge_2 on end # LAN3 - device ref gpp_bridge_3 on end # LAN4 - device ref gpp_bridge_4 on end # mPCIe slot 1 - end + device ref iommu on end + device ref gpp_bridge_0 on end # LAN1 + device ref gpp_bridge_1 on end # LAN2 + device ref gpp_bridge_2 on end # LAN3 + device ref gpp_bridge_3 on end # LAN4 + device ref gpp_bridge_4 on end # mPCIe slot 1 chip southbridge/amd/pi/hudson device ref xhci on end # XHCI HC0 muxed with EHCI 2 diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb index fb41fef0527b..75cc446e463f 100644 --- a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb @@ -1,16 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -chip northbridge/amd/pi/00730F01/root_complex +chip northbridge/amd/pi/00730F01 device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 - device ref iommu on end - device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) - device ref gpp_bridge_1 on end # LAN3 - device ref gpp_bridge_2 on end # LAN2 - device ref gpp_bridge_3 on end # LAN1 - device ref gpp_bridge_4 on end # mPCIe slot 1 - end + device ref iommu on end + device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) + device ref gpp_bridge_1 on end # LAN3 + device ref gpp_bridge_2 on end # LAN2 + device ref gpp_bridge_3 on end # LAN1 + device ref gpp_bridge_4 on end # mPCIe slot 1 chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus device ref xhci on end # XHCI HC0 muxed with EHCI 2 diff --git a/src/northbridge/amd/pi/00730F01/chipset.cb b/src/northbridge/amd/pi/00730F01/chipset.cb index 2ddfcebbf466..57f89c487075 100644 --- a/src/northbridge/amd/pi/00730F01/chipset.cb +++ b/src/northbridge/amd/pi/00730F01/chipset.cb @@ -1,22 +1,20 @@ # SPDX-License-Identifier: GPL-2.0-only -chip northbridge/amd/pi/00730F01/root_complex +chip northbridge/amd/pi/00730F01 device cpu_cluster 0 on end device domain 0 on - chip northbridge/amd/pi/00730F01 - device pci 0.0 alias gnb on end - device pci 0.2 alias iommu off end - device pci 1.0 alias gfx off end - device pci 1.1 alias gfx_hda off end - device pci 2.0 on end # Dummy Host Bridge, do not disable - device pci 2.1 alias gpp_bridge_0 off end - device pci 2.2 alias gpp_bridge_1 off end - device pci 2.3 alias gpp_bridge_2 off end - device pci 2.4 alias gpp_bridge_3 off end - device pci 2.5 alias gpp_bridge_4 off end - device pci 8.0 alias psp on end - end + device pci 0.0 alias gnb on end + device pci 0.2 alias iommu off end + device pci 1.0 alias gfx off end + device pci 1.1 alias gfx_hda off end + device pci 2.0 on end # Dummy Host Bridge, do not disable + device pci 2.1 alias gpp_bridge_0 off end + device pci 2.2 alias gpp_bridge_1 off end + device pci 2.3 alias gpp_bridge_2 off end + device pci 2.4 alias gpp_bridge_3 off end + device pci 2.5 alias gpp_bridge_4 off end + device pci 8.0 alias psp on end chip southbridge/amd/pi/hudson device pci 10.0 alias xhci off end diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index bafe5a581014..e8f7abdc3134 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -695,12 +695,6 @@ static void fam16_finalize(void *chip_info) } } -struct chip_operations northbridge_amd_pi_00730F01_ops = { - CHIP_NAME("AMD FAM16 Northbridge") - .enable_dev = 0, - .final = fam16_finalize, -}; - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned int hole_startk; @@ -886,9 +880,10 @@ static void root_complex_enable_dev(struct device *dev) } } -struct chip_operations northbridge_amd_pi_00730F01_root_complex_ops = { +struct chip_operations northbridge_amd_pi_00730F01_ops = { CHIP_NAME("AMD FAM16 Root Complex") .enable_dev = root_complex_enable_dev, + .final = fam16_finalize, }; /********************************************************************* -- cgit v1.2.3