From 1f44efc2028575fcf940ef188f62bf3730a3d81d Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Fri, 7 May 2021 21:25:17 +0200 Subject: soc/intel/skylake: Set proper defaults in chipset devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit LPC, P2SB and Power Management controller are always needed. Thus, enable them by default. Change-Id: I20b8cbe536da70fccc3d11e1eedf4a5e14bfc862 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/53925 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner --- src/soc/intel/skylake/chipset.cb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb index 428db67d3a6a..37100f037bc2 100644 --- a/src/soc/intel/skylake/chipset.cb +++ b/src/soc/intel/skylake/chipset.cb @@ -59,9 +59,9 @@ chip soc/intel/skylake device pci 1e.4 alias emmc off end # EMMC device pci 1e.5 alias sdio off end # SDIO device pci 1e.6 alias sdxc off end # SDXC - device pci 1f.0 alias lpc_espi off end # LPC Interface - device pci 1f.1 alias p2sb off end # P2SB - device pci 1f.2 alias pmc off end # Power Management Controller + device pci 1f.0 alias lpc_espi on end # LPC Interface + device pci 1f.1 alias p2sb on end # P2SB + device pci 1f.2 alias pmc on end # Power Management Controller device pci 1f.3 alias hda off end # Intel HDA device pci 1f.4 alias smbus off end # SMBus device pci 1f.5 alias fast_spi off end # PCH SPI -- cgit v1.2.3