From 4b97a134857f98c4c0378ab0118b75b5b6a482dc Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidi.lin@mediatek.com>
Date: Tue, 6 Apr 2021 14:10:53 +0800
Subject: mb/google/cherry: Configure TPM

Change-Id: I1d6ecdb31eef65d2e96d9251348390aa8598be6c
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/cherry/Kconfig     | 10 ++++++++++
 src/mainboard/google/cherry/bootblock.c |  3 +++
 src/mainboard/google/cherry/chromeos.c  |  6 ++++++
 3 files changed, 19 insertions(+)

diff --git a/src/mainboard/google/cherry/Kconfig b/src/mainboard/google/cherry/Kconfig
index b9c63ea9e671..7377c6c94afc 100644
--- a/src/mainboard/google/cherry/Kconfig
+++ b/src/mainboard/google/cherry/Kconfig
@@ -22,6 +22,8 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_SPI
+	select MAINBOARD_HAS_I2C_TPM_CR50 if VBOOT
+	select MAINBOARD_HAS_TPM2 if VBOOT
 
 config MAINBOARD_DIR
 	string
@@ -31,6 +33,14 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "Cherry" if BOARD_GOOGLE_CHERRY
 
+config DRIVER_TPM_I2C_BUS
+	hex
+	default 0x3
+
+config DRIVER_TPM_I2C_ADDR
+	hex
+	default 0x50
+
 # On MT8195 the SPI flash is actually using a SPI-NOR controller with its own bus.
 # The number here should be a virtual value as (SPI_BUS_NUMBER + 1).
 config BOOT_DEVICE_SPI_FLASH_BUS
diff --git a/src/mainboard/google/cherry/bootblock.c b/src/mainboard/google/cherry/bootblock.c
index dbc6c26e5e5a..93f0bce4baa2 100644
--- a/src/mainboard/google/cherry/bootblock.c
+++ b/src/mainboard/google/cherry/bootblock.c
@@ -3,6 +3,7 @@
 #include <bootblock_common.h>
 #include <device/mmio.h>
 #include <soc/gpio.h>
+#include <soc/i2c.h>
 #include <soc/spi.h>
 
 #include "gpio.h"
@@ -36,7 +37,9 @@ static void nor_set_gpio_pinmux(void)
 
 void bootblock_mainboard_init(void)
 {
+	mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS);
 	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
 	nor_set_gpio_pinmux();
 	setup_chromeos_gpios();
+	gpio_eint_configure(GPIO_GSC_AP_INT, IRQ_TYPE_EDGE_RISING);
 }
diff --git a/src/mainboard/google/cherry/chromeos.c b/src/mainboard/google/cherry/chromeos.c
index 1a869a3fe079..03e44d5ac220 100644
--- a/src/mainboard/google/cherry/chromeos.c
+++ b/src/mainboard/google/cherry/chromeos.c
@@ -3,6 +3,7 @@
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <gpio.h>
+#include <security/tpm/tis.h>
 
 #include "gpio.h"
 
@@ -28,3 +29,8 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 	};
 	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
+
+int tis_plat_irq_status(void)
+{
+	return gpio_eint_poll(GPIO_GSC_AP_INT);
+}
-- 
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