From 70a1ef071693af72061f5eef1ee24e56712c55a1 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Tue, 4 Jan 2022 11:09:41 +0000 Subject: mb/starlabs/labtop: Reconfigure CNVi GPIOs Reconfigure the CNVi GPIO's so that they are configured correctly. The original configuration was based on the AMI firmware, and whilst it worked, it wasn't optimal. Signed-off-by: Sean Rhodes Change-Id: I9fc9963e91da0267c8740fee20a3ec41895b4953 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60758 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/mainboard/starlabs/labtop/variants/tgl/gpio.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/starlabs/labtop/variants/tgl/gpio.c b/src/mainboard/starlabs/labtop/variants/tgl/gpio.c index 81de01e32503..559de8d4d32e 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/gpio.c +++ b/src/mainboard/starlabs/labtop/variants/tgl/gpio.c @@ -279,15 +279,15 @@ const struct pad_config gpio_table[] = { /* F0: CNV_BRI_DT_BT_UART0_RTS_R */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* F1: CNV_BRI_RSP_BT_UART0_RX_R */ - PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* F2: CNV_RGI_DT_BT_UART0_TX_R */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* F3: CNV_RGI_RSP_BT_UART0_CTS */ - PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* F4: Not Connected */ PAD_NC(GPP_F4, NONE), /* F5: GPPC_F5_MODEM_CLKREQ */ - PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), + PAD_NC(GPP_F5, NONE), /* F6: Not Connected */ PAD_NC(GPP_F6, NONE), /* F7: BIOS_REC */ -- cgit v1.2.3