From 737ad67d122b24f8309ad76b66b5d7a26873eb39 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Thu, 24 Feb 2022 11:49:52 -0700 Subject: soc/amd/common/psp_verstage: Add missing post codes on S0i3 resume We print these out in the normal flow, so lets add them for S0i3 resume as well. BUG=b:221231786 TEST=Perform suspend/resume cycle on guybrush and verify we get the new POST codes. Signed-off-by: Raul E Rangel Change-Id: Ia7d607453d58084868cfa50770fd0f370b2ea2bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62346 Tested-by: build bot (Jenkins) Reviewed-by: Rob Barnes Reviewed-by: Karthik Ramasubramanian --- src/soc/amd/common/psp_verstage/psp_verstage.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 7359a44e52d5..05f0cdac3940 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -251,7 +251,11 @@ void Main(void) svc_get_boot_mode(&bootmode); if (bootmode == PSP_BOOT_MODE_S0i3_RESUME) { psp_verstage_s0i3_resume(); + + post_code(POSTCODE_UNMAP_FCH_DEVICES); unmap_fch_devices(); + + post_code(POSTCODE_LEAVING_VERSTAGE); svc_exit(0); } -- cgit v1.2.3