From 8665d885614178abc27c56d30a42c537524cd167 Mon Sep 17 00:00:00 2001 From: Xi Chen Date: Thu, 18 Aug 2022 10:00:59 +0800 Subject: soc/mediatek: Move dpm_4ch.c to common MT8195 and MT8188 share the same dpm_4ch.c, so we move it to common folder. TEST=build pass BUG=b:236331724 Signed-off-by: Xi Chen Change-Id: I13406707d3b331ced57af62f4ba4f365e9ac4f84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66966 Reviewed-by: Yidi Lin Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/common/dpm_4ch.c | 89 ++++++++++++++++++++++++++++++++++++ src/soc/mediatek/mt8195/Makefile.inc | 2 +- src/soc/mediatek/mt8195/dpm_4ch.c | 89 ------------------------------------ 3 files changed, 90 insertions(+), 90 deletions(-) create mode 100644 src/soc/mediatek/common/dpm_4ch.c delete mode 100644 src/soc/mediatek/mt8195/dpm_4ch.c diff --git a/src/soc/mediatek/common/dpm_4ch.c b/src/soc/mediatek/common/dpm_4ch.c new file mode 100644 index 000000000000..f13337d8b7b1 --- /dev/null +++ b/src/soc/mediatek/common/dpm_4ch.c @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +static struct dpm_regs *const mtk_dpm2 = (void *)DPM_CFG_BASE2; + +static int wake_dpm_sram_up(void) +{ + int loop = 100; + + /* TODO: convert to new APIs (SET32_BITFIELDS/READ32_BITFIELD) */ + setbits32(&mtk_spm->dramc_mcu_sram_con, DRAMC_MCU_SRAM_SLEEP_B_LSB); + setbits32(&mtk_spm->dramc_mcu2_sram_con, DRAMC_MCU2_SRAM_SLEEP_B_LSB); + + while (loop > 0 && + ((read32(&mtk_spm->dramc_mcu_sram_con) & + DRAMC_MCU_SRAM_SLEEP_B_LSB) == 0 || + (read32(&mtk_spm->dramc_mcu2_sram_con) & + DRAMC_MCU2_SRAM_SLEEP_B_LSB) == 0)) { + mdelay(1); + --loop; + } + + if (loop == 0) { + printk(BIOS_ERR, "failed to wake DPM up.\n"); + return -1; + } + + setbits32(&mtk_spm->dramc_mcu_sram_con, DRAMC_MCU_SRAM_ISOINT_B_LSB); + setbits32(&mtk_spm->dramc_mcu2_sram_con, DRAMC_MCU2_SRAM_ISOINT_B_LSB); + + return 0; +} + +static void dpm_mtcoms_sleep_on(void) +{ + /* DPM MTCMOS sleep on */ + write32(&mtk_spm->dpm0_pwr_con, 0x0000204d); + write32(&mtk_spm->dpm1_pwr_con, 0x0000204d); + mdelay(1); + write32(&mtk_spm->dpm0_pwr_con, 0x0000224d); + write32(&mtk_spm->dpm1_pwr_con, 0x0000224d); + mdelay(1); + clrbits32(&mtk_dpm->sw_rstn, DPM_SW_RSTN_RESET); + clrbits32(&mtk_dpm2->sw_rstn, DPM_SW_RSTN_RESET); +} + +static struct mtk_mcu dpm_mcu_4ch[] = { + { + .firmware_name = CONFIG_DPM_DM_FIRMWARE, + .run_address = (void *)DPM_DM_SRAM_BASE2, + }, + { + .firmware_name = CONFIG_DPM_PM_FIRMWARE, + .run_address = (void *)DPM_PM_SRAM_BASE2, + .priv = mtk_dpm2, + .reset = dpm_reset, + }, +}; + +int dpm_4ch_init(void) +{ + dpm_mtcoms_sleep_on(); + if (wake_dpm_sram_up()) + return -1; + return 0; +} + +int dpm_4ch_para_setting(void) +{ + int i; + struct mtk_mcu *dpm; + + for (i = 0; i < ARRAY_SIZE(dpm_mcu_4ch); i++) { + dpm = &dpm_mcu_4ch[i]; + dpm->load_buffer = _dram_dma; + dpm->buffer_size = REGION_SIZE(dram_dma); + if (mtk_init_mcu(dpm)) + return -1; + } + + return 0; +} diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index b8c36d162576..c9613bff6c8f 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -44,7 +44,7 @@ ramstage-y += ../common/ddp.c ddp.c ramstage-y += devapc.c ramstage-y += ../common/dfd.c ramstage-y += ../common/dpm.c -ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += dpm_4ch.c +ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c ramstage-y += dp_intf.c dptx.c dptx_hal.c ramstage-y += emi.c ramstage-y += hdmi.c diff --git a/src/soc/mediatek/mt8195/dpm_4ch.c b/src/soc/mediatek/mt8195/dpm_4ch.c deleted file mode 100644 index f13337d8b7b1..000000000000 --- a/src/soc/mediatek/mt8195/dpm_4ch.c +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include - -static struct dpm_regs *const mtk_dpm2 = (void *)DPM_CFG_BASE2; - -static int wake_dpm_sram_up(void) -{ - int loop = 100; - - /* TODO: convert to new APIs (SET32_BITFIELDS/READ32_BITFIELD) */ - setbits32(&mtk_spm->dramc_mcu_sram_con, DRAMC_MCU_SRAM_SLEEP_B_LSB); - setbits32(&mtk_spm->dramc_mcu2_sram_con, DRAMC_MCU2_SRAM_SLEEP_B_LSB); - - while (loop > 0 && - ((read32(&mtk_spm->dramc_mcu_sram_con) & - DRAMC_MCU_SRAM_SLEEP_B_LSB) == 0 || - (read32(&mtk_spm->dramc_mcu2_sram_con) & - DRAMC_MCU2_SRAM_SLEEP_B_LSB) == 0)) { - mdelay(1); - --loop; - } - - if (loop == 0) { - printk(BIOS_ERR, "failed to wake DPM up.\n"); - return -1; - } - - setbits32(&mtk_spm->dramc_mcu_sram_con, DRAMC_MCU_SRAM_ISOINT_B_LSB); - setbits32(&mtk_spm->dramc_mcu2_sram_con, DRAMC_MCU2_SRAM_ISOINT_B_LSB); - - return 0; -} - -static void dpm_mtcoms_sleep_on(void) -{ - /* DPM MTCMOS sleep on */ - write32(&mtk_spm->dpm0_pwr_con, 0x0000204d); - write32(&mtk_spm->dpm1_pwr_con, 0x0000204d); - mdelay(1); - write32(&mtk_spm->dpm0_pwr_con, 0x0000224d); - write32(&mtk_spm->dpm1_pwr_con, 0x0000224d); - mdelay(1); - clrbits32(&mtk_dpm->sw_rstn, DPM_SW_RSTN_RESET); - clrbits32(&mtk_dpm2->sw_rstn, DPM_SW_RSTN_RESET); -} - -static struct mtk_mcu dpm_mcu_4ch[] = { - { - .firmware_name = CONFIG_DPM_DM_FIRMWARE, - .run_address = (void *)DPM_DM_SRAM_BASE2, - }, - { - .firmware_name = CONFIG_DPM_PM_FIRMWARE, - .run_address = (void *)DPM_PM_SRAM_BASE2, - .priv = mtk_dpm2, - .reset = dpm_reset, - }, -}; - -int dpm_4ch_init(void) -{ - dpm_mtcoms_sleep_on(); - if (wake_dpm_sram_up()) - return -1; - return 0; -} - -int dpm_4ch_para_setting(void) -{ - int i; - struct mtk_mcu *dpm; - - for (i = 0; i < ARRAY_SIZE(dpm_mcu_4ch); i++) { - dpm = &dpm_mcu_4ch[i]; - dpm->load_buffer = _dram_dma; - dpm->buffer_size = REGION_SIZE(dram_dma); - if (mtk_init_mcu(dpm)) - return -1; - } - - return 0; -} -- cgit v1.2.3