From 89ae6b8fc2901b56dd1839a2d569493ce668a32c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 21 Mar 2020 13:23:32 +0100 Subject: nb/intel/sandybridge: Use cached CPUID Now that we have it, we might as well pass it around. Tested on Asus P8Z77-V LX2, still boots fine. Change-Id: Ia5aa2f932321983f11d2f8869aa624832afe9347 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39721 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/raminit_common.c | 9 +++------ src/northbridge/intel/sandybridge/raminit_common.h | 2 +- src/northbridge/intel/sandybridge/raminit_ivy.c | 2 +- src/northbridge/intel/sandybridge/raminit_sandy.c | 2 +- 4 files changed, 6 insertions(+), 9 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 9eb60c74c91b..41d683b18aad 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -168,15 +168,14 @@ void dram_xover(ramctr_timing *ctrl) static void dram_odt_stretch(ramctr_timing *ctrl, int channel) { - u32 addr, cpu, stretch; + u32 addr, stretch; stretch = ctrl->ref_card_offset[channel]; /* * ODT stretch: * Delay ODT signal by stretch value. Useful for multi DIMM setups on the same channel. */ - cpu = cpu_get_cpuid(); - if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) { + if (IS_SANDY_CPU(ctrl->cpu) && IS_SANDY_CPU_C(ctrl->cpu)) { if (stretch == 2) stretch = 3; @@ -2992,10 +2991,8 @@ void set_scrambling_seed(ramctr_timing *ctrl) } } -void set_wmm_behavior(void) +void set_wmm_behavior(const u32 cpu) { - u32 cpu = cpu_get_cpuid(); - if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) { MCHBAR32(SC_WDBWM) = 0x141d1519; } else { diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 0cbac8ae2099..0ff926505232 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -181,7 +181,7 @@ void normalize_training(ramctr_timing *ctrl); void write_controller_mr(ramctr_timing *ctrl); int channel_test(ramctr_timing *ctrl); void set_scrambling_seed(ramctr_timing *ctrl); -void set_wmm_behavior(void); +void set_wmm_behavior(const u32 cpu); void prepare_training(ramctr_timing *ctrl); void set_read_write_timings(ramctr_timing *ctrl); void set_normal_operation(ramctr_timing *ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 06d23825b636..a714e535b49a 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -609,7 +609,7 @@ int try_init_dram_ddr3_ivb(ramctr_timing *ctrl, int fast_boot, int s3_resume, in MCHBAR32(SCHED_CBIT) = 0x10100005; /* Set up watermarks and starvation counter */ - set_wmm_behavior(); + set_wmm_behavior(ctrl->cpu); /* Clear IO reset bit */ MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5); diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c index c554c3aa89f6..a823d503984e 100644 --- a/src/northbridge/intel/sandybridge/raminit_sandy.c +++ b/src/northbridge/intel/sandybridge/raminit_sandy.c @@ -433,7 +433,7 @@ int try_init_dram_ddr3_snb(ramctr_timing *ctrl, int fast_boot, int s3_resume, in MCHBAR32(SCHED_CBIT) = 0x10100005; /* Set up watermarks and starvation counter */ - set_wmm_behavior(); + set_wmm_behavior(ctrl->cpu); /* Clear IO reset bit */ MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5); -- cgit v1.2.3