From 92c2ccda0cab63b989582584392565fcc93d4def Mon Sep 17 00:00:00 2001 From: Elyes Haouas Date: Thu, 24 Feb 2022 07:22:01 +0100 Subject: sb/intel/ibexpeak/early_pch.c: Use PCI_BASE_ADDRESS_0 macro Signed-off-by: Elyes Haouas Change-Id: If74e1db623d65d639041d49caf0ca1b6c0e1f2ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/62326 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/southbridge/intel/ibexpeak/early_pch.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index 9edbcf6aa7a9..4df47f3cf17d 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -48,7 +48,8 @@ void ibexpeak_setup_bars(void) outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06); printk(BIOS_DEBUG, " done.\n"); - pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR); + pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_BASE_ADDRESS_0, + (uintptr_t)DEFAULT_HECIBAR); pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } -- cgit v1.2.3