From 9341920453a4538f83d3e707fc457e0038a121d6 Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Wed, 12 Jan 2022 13:31:21 +0900 Subject: mb/google/dedede/var/bugzzy: Set core display clock to 172.8 MHz When using the default initial core display clock frequency (648MHz), Jasper Lake board might have a rare stability issue where the startup of Chrome OS in secure mode may hang during re-initializing display in kernel graphic driver. Bugzzy didn't show this problem so far, but Intel recommends slowing the initial core display clock frequency down to 172.8 MHz to prevent this potential problem. Depend on CL: https://review.coreboot.org/c/coreboot/+/60009 The CdClock=0xff is set in dedede baseboard, and we overwrite it as 0x0 (172.8 MHz) for bugzzy. BUG=None BRANCH=dedede TEST=Build firmware and check the DUTs can boot up in secure mode well. Change-Id: I592b2d7c814881074bd2fef9906f2450326c1fcd Signed-off-by: Seunghwan Kim Reviewed-on: https://review.coreboot.org/c/coreboot/+/61022 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/dedede/variants/bugzzy/overridetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb index b56fb30fbacd..49f1e651f1ce 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb @@ -2,6 +2,9 @@ chip soc/intel/jasperlake # MIPI display panel register "DdiPortAConfig" = "2" # DdiPortMipiDsi + # Core Display Clock Frequency selection + register "cd_clock" = "CD_CLOCK_172_8_MHZ" + # Enable Acoustic noise mitigation and set slew rate to 1/8 # Rest of the parameters are 0 by default. register "AcousticNoiseMitigation" = "1" -- cgit v1.2.3