From a643e212c28614da73b08feb47bdbe772385a437 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 9 Apr 2021 20:53:19 +0200 Subject: soc/amd/common/block/gpio: remove SoC type check in gpio_fill_wake_state Verified that all accessed registers exist in all SoCs that use this code (Carrizo, Mullins, Stoneyridge, Picasso and Cezanne at the moment) and that the bit definitions match as well. Also at the time of writing this patch only Picasso calls gpio_fill_wake_state, so dropping the check won't change behavior. This also avoids having SoC specific code that doesn't get selected by Kconfig options in the common AMD SoC directory and also avoids having to add a check for SOC_AMD_CEZANNE to support this functionality on Cezanne in a follow-up patch. Signed-off-by: Felix Held Change-Id: If770780a67776daf81744db1b635ffd402653a47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52223 Reviewed-by: Raul Rangel Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/gpio_banks/gpio.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 186df5093d46..1d664cb54a3e 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -347,10 +347,6 @@ void gpio_fill_wake_state(struct gpio_wake_state *state) const uint8_t stat1 = GPIO_WAKE_STAT_1 / sizeof(uint32_t); const uint8_t control_switch = GPIO_MASTER_SWITCH / sizeof(uint32_t); - /* Register fields and gpio availability need to be confirmed on other chipsets. */ - if (!CONFIG(SOC_AMD_PICASSO)) - dead_code(); - memset(state, 0, sizeof(*state)); state->control_switch = gpio_read32(control_switch); -- cgit v1.2.3