From a66b469107b10b3013fb1003c4821f0fb666c965 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 19 Apr 2023 10:12:38 +0200 Subject: vendorcode/mediatek/mt8195: Make order of operators more explicit Clang warns about this. Change-Id: I9a19f33df64a63e51e3dadac4aae28a8bb12121d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/74551 Tested-by: build bot (Jenkins) Reviewed-by: Elyes Haouas --- src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c b/src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c index 6634e48e673e..14ea0b368dc3 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c +++ b/src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c @@ -116,7 +116,7 @@ static void lp4_dram_init_single_rank(DRAMC_CTX_T *p,LP4_DRAM_CONFIG_T *tr,U8 ra LP4_MRS(p, 1, MR1 , rank); LP4_MRS(p, 2, MR2 , rank); - MR3 = ((!tr->DBI_WR & 1)<<7) | ((!tr->DBI_RD & 1)<<6) | (( PDDS & 7)<<3) | ((PPRP & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0); + MR3 = (((!tr->DBI_WR) & 1)<<7) | (((!tr->DBI_RD) & 1)<<6) | (( PDDS & 7)<<3) | ((PPRP & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0); LP4_MRS(p, 3, MR3 , rank); LP4_MRS(p, 11, MR11 , rank); LP4_MRS(p, 12, MR12 , rank); -- cgit v1.2.3