From c423293d200cfa8ff7162a07fcd365a58347ab7e Mon Sep 17 00:00:00 2001 From: Ian Feng Date: Fri, 17 Apr 2020 16:45:08 +0800 Subject: mb/google/dedede: Disable dynamic clock gating for cr50's GPIO Disable dynamic clock gating for the community cr50's IRQ lives on. That IRQ is pulsed very quickly, and with clock gating enabled pulses tend to be missed. This is expecially true on the default 0.0.22 firmware that cr50 comes with out of the factory. BUG=b:154178408 b:154293730 BRANCH=None TEST=build waddledoo successful and Linux has no TPM IRQ timeout error. Signed-off-by: Ian Feng Change-Id: I2b1b3ee59ebf6adce0653e7550b457e02d3c87df Reviewed-on: https://review.coreboot.org/c/coreboot/+/40480 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index f030b20cecee..cfe221f9948a 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -118,6 +118,14 @@ chip soc/intel/jasperlake # Select eDP for port A register "DdiPortAConfig" = "1" + # Disable PM to allow for shorter irq pulses + register "gpio_override_pm" = "1" + register "gpio_pm[0]" = "0" + register "gpio_pm[1]" = "0" + register "gpio_pm[2]" = "0" + register "gpio_pm[3]" = "0" + register "gpio_pm[4]" = "0" + # Enable HPD for DDI ports B/C register "DdiPortBHpd" = "1" register "DdiPortCHpd" = "1" -- cgit v1.2.3