From c5f1dc96bf0b18245d7986463ae56958c44d24f2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 10 Apr 2021 22:51:15 +0200 Subject: mb/*: drop LPC generic range for port 80 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have to be set up as generic range. Drop the entries from the devicetrees. Change-Id: I8a54d3c35a321a2d57bd846662f7339eff53e5a8 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/52237 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/51nb/x210/devicetree.cb | 5 ++--- src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb | 3 +-- src/mainboard/intel/adlrvp/devicetree.cb | 1 - src/mainboard/intel/adlrvp/devicetree_m.cb | 1 - src/mainboard/libretrend/lt1000/devicetree.cb | 1 - src/mainboard/purism/librem_bdw/devicetree.cb | 1 - src/mainboard/purism/librem_skl/devicetree.cb | 1 - src/mainboard/razer/blade_stealth_kbl/devicetree.cb | 5 ++--- src/mainboard/system76/gaze15/devicetree.cb | 7 +++---- src/mainboard/system76/lemp9/devicetree.cb | 8 +++----- src/mainboard/system76/oryp5/devicetree.cb | 7 +++---- 11 files changed, 14 insertions(+), 26 deletions(-) diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 433bc22fbbe9..1a1d0129baf8 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -26,9 +26,8 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x000c0081" - register "gen2_dec" = "0x000c0681" - register "gen3_dec" = "0x000c1641" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" # Disable DPTF register "dptf_enable" = "0" diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index 29f57bd64327..0a0cdf43a1e9 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -114,8 +114,7 @@ chip soc/intel/skylake device pci 1f.0 on # LPC Interface register "gen1_dec" = "0x000c0681" register "gen2_dec" = "0x000c1641" - register "gen3_dec" = "0x000c0081" - register "gen4_dec" = "0x00040069" + register "gen3_dec" = "0x00040069" register "serirq_mode" = "SERIRQ_CONTINUOUS" chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 57d78de9ce94..5ca846811885 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -41,7 +41,6 @@ chip soc/intel/alderlake register "gen2_dec" = "0x000c0201" # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - register "gen4_dec" = "0x000c0081" # This disabled autonomous GPIO power management, otherwise # old cr50 FW only supports short pulses; need to clarify diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 7c691638c7fc..c6c253797864 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -34,7 +34,6 @@ chip soc/intel/alderlake register "gen2_dec" = "0x000c0201" # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - register "gen4_dec" = "0x000c0081" register "PrmrrSize" = "0" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 9fedde5db894..5e5c9beddf53 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -28,7 +28,6 @@ chip soc/intel/skylake register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff - register "gen4_dec" = "0x000c0081" # 0x80 - 0x8f # Disable DPTF register "dptf_enable" = "0" diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index 9995f6bd6f61..b35d98469c51 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -29,7 +29,6 @@ chip soc/intel/broadwell chip soc/intel/broadwell/pch # EC host command ranges are in 0x380-0x383 & 0x80-0x8f register "gen1_dec" = "0x00000381" - register "gen2_dec" = "0x000c0081" device pci 13.0 off end # Smart Sound Audio DSP device pci 14.0 on end # USB3 XHCI diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index c3a9567ccfe6..47a9a5cbc6ff 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -36,7 +36,6 @@ chip soc/intel/skylake # EC host command ranges are in 0x380-0x383 & 0x80-0x8f register "gen1_dec" = "0x00000381" - register "gen2_dec" = "0x000c0081" # Disable DPTF register "dptf_enable" = "0" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index a358fb837462..a4951fe9debd 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -15,9 +15,8 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x000c0081" - register "gen2_dec" = "0x000c0681" - register "gen3_dec" = "0x000c1641" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" # Disable DPTF register "dptf_enable" = "0" diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index e4ca948ff0b4..5165f61a66d1 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -194,10 +194,9 @@ chip soc/intel/cannonlake device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 device pci 1f.0 on # LPC Interface - register "gen1_dec" = "0x000c0081" - register "gen2_dec" = "0x00040069" - register "gen3_dec" = "0x00fc0e01" - register "gen4_dec" = "0x00fc0f01" + register "gen1_dec" = "0x00040069" + register "gen2_dec" = "0x00fc0e01" + register "gen3_dec" = "0x00fc0f01" chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index a0b6403a22ca..80f0ef4b9fc3 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -178,14 +178,12 @@ chip soc/intel/cannonlake device pci 1e.3 off end # GSPI #1 device pci 1f.0 on # LPC Interface # LPC configuration from lspci -s 1f.0 -xxx - # Address 0x84: Decode 0x80 - 0x8F (Port 80) - register "gen1_dec" = "0x000c0081" # Address 0x88: Decode 0x68 - 0x6F (EC PM channel) - register "gen2_dec" = "0x00040069" + register "gen1_dec" = "0x00040069" # Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command) - register "gen3_dec" = "0x00fc0E01" + register "gen2_dec" = "0x00fc0E01" # Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug) - register "gen4_dec" = "0x00fc0F01" + register "gen3_dec" = "0x00fc0F01" chip drivers/pc80/tpm # TPM device pnp 0c31.0 on end end diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index 6cf5c94ea810..2b08909b6703 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -182,10 +182,9 @@ chip soc/intel/cannonlake device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 device pci 1f.0 on # LPC Interface - register "gen1_dec" = "0x000c0081" - register "gen2_dec" = "0x00040069" - register "gen3_dec" = "0x00fc0e01" - register "gen4_dec" = "0x00fc0f01" + register "gen1_dec" = "0x00040069" + register "gen2_dec" = "0x00fc0e01" + register "gen3_dec" = "0x00fc0f01" chip drivers/pc80/tpm device pnp 0c31.0 on end end -- cgit v1.2.3