From d3b8321563efe07855687c9803bec3911b33edb5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 28 Apr 2022 13:10:22 +0200 Subject: superio/nuvoton/nct6687d: Add ramstage driver and ACPI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TEST=Boot MSI PRO Z690-A WIFI DDR4 with SP1, KBC and EC exposed to OS via ACPI. Configure SP1, ACPI, KBC and EC devices via devicetree. Signed-off-by: Michał Żygowski Change-Id: Ia489a39956c1448c7f11845ecc9e1df83ccb25ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/63927 Reviewed-by: Krystian Hebel Tested-by: build bot (Jenkins) --- src/superio/nuvoton/nct6687d/Makefile.inc | 3 + src/superio/nuvoton/nct6687d/acpi/superio.asl | 175 ++++++++++++++++++++++++++ src/superio/nuvoton/nct6687d/superio.c | 92 ++++++++++++++ 3 files changed, 270 insertions(+) create mode 100644 src/superio/nuvoton/nct6687d/Makefile.inc create mode 100644 src/superio/nuvoton/nct6687d/acpi/superio.asl create mode 100644 src/superio/nuvoton/nct6687d/superio.c diff --git a/src/superio/nuvoton/nct6687d/Makefile.inc b/src/superio/nuvoton/nct6687d/Makefile.inc new file mode 100644 index 000000000000..d4785f726e69 --- /dev/null +++ b/src/superio/nuvoton/nct6687d/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += superio.c diff --git a/src/superio/nuvoton/nct6687d/acpi/superio.asl b/src/superio/nuvoton/nct6687d/acpi/superio.asl new file mode 100644 index 000000000000..ebddeaeb08bf --- /dev/null +++ b/src/superio/nuvoton/nct6687d/acpi/superio.asl @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the NCT6687D SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices. + * + * LDN State + * 0x1 PP Implemented, untested + * 0x2 SP1 Implemented, untested + * 0x3 SP1 Implemented, untested + * 0x5 KBC Implemented, untested + * 0x8 GPIO Implemented, untested + * 0xb EC Implemented, untested + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * NCT6687D_SHOW_PP If defined, the parallel port will be exposed. + * NCT6687D_SHOW_SP1 If defined, Serial Port 1 will be exposed. + * NCT6687D_SHOW_SP2 If defined, Serial Port 2 will be exposed. + * NCT6687D_SHOW_KBC If defined, the Keyboard Controller will be exposed. + * NCT6687D_SHOW_GPIO If defined, GPIO support will be exposed. + * NCT6687D_SHOW_EC If defined, the Environment Controller will be exposed. + */ + +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME NCT6687D +#include + +#undef PNP_DEFAULT_PSC +#define PNP_DEFAULT_PSC Return (0) /* no power management */ + +Device(SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Nuvoton NCT6687D Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8, + } + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + ACT1, 1, /* Logical device activation */ + ACT2, 1, /* Logical device activation */ + ACT3, 1, /* Logical device activation */ + ACT4, 1, /* Logical device activation */ + ACT5, 1, /* Logical device activation */ + ACT6, 1, /* Logical device activation */ + ACT7, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + Offset (0x64), + PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */ + PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + Offset (0x72), + PNP_IRQ1, 8, /* Second IRQ */ + Offset (0x74), + PNP_DMA0, 8, /* DRQ */ + } + + Method (_CRS) + { + /* Announce the used I/O ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #undef PNP_EXIT_SPECIAL_REG + #undef PNP_EXIT_SPECIAL_VAL + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x87 + #define PNP_EXIT_MAGIC_1ST 0xaa + #include + +#ifdef NCT6687D_SHOW_PP + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + /* + * The extra code required to dynamically reflect ECP in the HID + * isn't currently justified, so the HID is hardcoded as not + * using ECP. "PNP0401" would indicate ECP. + */ + #define SUPERIO_PNP_HID "PNP0400" + #define SUPERIO_PNP_LDN 1 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #define SUPERIO_PNP_IRQ0 + #define SUPERIO_PNP_DMA + #include +#endif + +#ifdef NCT6687D_SHOW_SP1 + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #include +#endif + +#ifdef NCT6687D_SHOW_SP2 + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 3 + #include +#endif + +#ifdef NCT6687D_SHOW_KBC + #undef SUPERIO_KBC_LDN + #undef SUPERIO_KBC_PS2M + #undef SUPERIO_KBC_PS2LDN + #define SUPERIO_KBC_LDN 5 + #define SUPERIO_KBC_PS2M + #include +#endif + +#ifdef NCT6687D_SHOW_EC + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #define SUPERIO_PNP_LDN 11 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #define SUPERIO_PNP_IRQ0 + #include +#endif + +} diff --git a/src/superio/nuvoton/nct6687d/superio.c b/src/superio/nuvoton/nct6687d/superio.c new file mode 100644 index 000000000000..479565911837 --- /dev/null +++ b/src/superio/nuvoton/nct6687d/superio.c @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +#include "nct6687d.h" + +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2 + +/* 0xeb register definitions */ +#define NCT6687D_ACPI_POWER_LOSS_CONTROL_MASK 0x60 +#define NCT6687D_ACPI_POWER_LOSS_CONTROL_SHIFT 5 +#define NCT6687D_ACPI_POWER_ALWAYS_OFF (0 << NCT6687D_ACPI_POWER_LOSS_CONTROL_SHIFT) +#define NCT6687D_ACPI_POWER_ALWAYS_ON (1 << NCT6687D_ACPI_POWER_LOSS_CONTROL_SHIFT) +#define NCT6687D_ACPI_POWER_PREV_STATE (2 << NCT6687D_ACPI_POWER_LOSS_CONTROL_SHIFT) +#define NCT6687D_ACPI_POWER_USER_DEFINED (3 << NCT6687D_ACPI_POWER_LOSS_CONTROL_SHIFT) + +static void nct6687d_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + /* TODO: Might potentially need code for EC, GPIOs, etc. */ + case NCT6687D_KBC: + pc_keyboard_init(PROBE_AUX_DEVICE); + break; + case NCT6687D_ACPI: + uint8_t byte; + uint8_t power_status; + /* Set power state after power fail */ + power_status = get_uint_option("power_on_after_fail", + CONFIG_MAINBOARD_POWER_FAILURE_STATE); + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + byte = pnp_read_config(dev, 0xeb); + byte &= ~NCT6687D_ACPI_POWER_LOSS_CONTROL_MASK; + if (power_status == MAINBOARD_POWER_ON) + byte |= NCT6687D_ACPI_POWER_ALWAYS_ON; + else if (power_status == MAINBOARD_POWER_KEEP) + byte |= NCT6687D_ACPI_POWER_PREV_STATE; + pnp_write_config(dev, 0xeb, byte); + pnp_exit_conf_mode(dev); + printk(BIOS_INFO, "set power %s after power fail\n", + power_status ? "on" : "off"); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct6687d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, NCT6687D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0, 0x0FF8,}, + { NULL, NCT6687D_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0FF8, }, + { NULL, NCT6687D_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1, 0x0FF8, }, + { NULL, NCT6687D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0, + 0x0FFF, 0x0FFF, }, + { NULL, NCT6687D_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | PNP_MSC3, + 0x0FF8, }, + { NULL, NCT6687D_GPIO_0_7, PNP_IO0 | PNP_IRQ0, 0x0FF0,}, + { NULL, NCT6687D_P80_UART}, + { NULL, NCT6687D_GPIO_8_9_AF}, + { NULL, NCT6687D_ACPI, PNP_IO0 | PNP_IRQ0, 0x0FF8,}, + { NULL, NCT6687D_EC, PNP_IO0 | PNP_IRQ0, 0x0FF8,}, + { NULL, NCT6687D_RTC}, + { NULL, NCT6687D_SLEEP_PWR}, + { NULL, NCT6687D_TACH_PWM}, + { NULL, NCT6687D_FREG}, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct6687d_ops = { + CHIP_NAME("NUVOTON NCT6687D Super I/O") + .enable_dev = enable_dev, +}; -- cgit v1.2.3