From edc6da2de9cc491a03cfa335879829efb0446b74 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Wed, 7 Apr 2021 10:18:43 +0530 Subject: mb/intel/adlrvp: Enable HECI1 communication The patch enables HECI1 interface to allow OS applications to communicate with CSE. BUG=None TEST=Build and boot ADLRVP. Run lspci and check pcie device (00:16.0) Signed-off-by: Sridhar Siricilla Change-Id: I34ff842481bdfc7933a76555ff0fd70f4fbbb9a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52149 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi Reviewed-by: Maulik V Vaghela --- src/mainboard/intel/adlrvp/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index cade987313d5..57d78de9ce94 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -12,6 +12,9 @@ chip soc/intel/alderlake register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" + # Enable HECI1 interface + register "HeciEnabled" = "1" + # FSP configuration # Enable CNVi BT -- cgit v1.2.3