From fd7ed87746d763feff7d26dba9598b505e8750c1 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Tue, 4 May 2021 15:42:09 -0600 Subject: soc/amd/cezanne: Populate PCI_INTR registers This uses the new FSP PCI methods to pull the routing table and populate the pirq data structure. BUG=b:184766519 TEST=Boot guybrush and verify we get Got IRQ 0x1F (disabled) messages Signed-off-by: Raul E Rangel Change-Id: Ie21229cc2fb4fd5b85c0b9e933f7b43af24864b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52914 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/amd/cezanne/Kconfig | 1 + src/soc/amd/cezanne/fch.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 1d769be84dce..dafc26f4ef72 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -61,6 +61,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE + select SOC_AMD_COMMON_FSP_PCI select SSE2 select UDK_2017_BINDING select X86_AMD_FIXED_MTRRS diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 88265abb0496..028ffec17b7e 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -131,6 +131,12 @@ static void set_pci_irqs(void *unused) { /* Write PCI_INTR regs 0xC00/0xC01 */ write_pci_int_table(); + + /* pirq_data is consumed by `write_pci_cfg_irqs` */ + populate_pirq_data(); + + /* Write IRQs for all devicetree enabled devices */ + write_pci_cfg_irqs(); } /* -- cgit v1.2.3