From 8c678cf46a2bc9716a84609615b602422a233a9e Mon Sep 17 00:00:00 2001 From: Philipp Deppenwiese Date: Fri, 10 Aug 2018 16:15:14 -0700 Subject: mainboard/opencellular/elgon: Add mainboard support Tested on Elgon EVT board and boots into GNU/Linux. TODO: * Add hard reset function for VBOOT. * Add EC code * Add SPI flash write protection Change-Id: I9b809306cc48facbade5dc63846c4532b397e0b5 Signed-off-by: Philipp Deppenwiese Reviewed-on: https://review.coreboot.org/28024 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese --- Documentation/mainboard/opencellular/elgon.md | 72 ++++++++++++++++++++++++ Documentation/mainboard/opencellular/elgon1.png | Bin 0 -> 813773 bytes Documentation/mainboard/opencellular/elgon2.png | Bin 0 -> 730981 bytes 3 files changed, 72 insertions(+) create mode 100644 Documentation/mainboard/opencellular/elgon.md create mode 100644 Documentation/mainboard/opencellular/elgon1.png create mode 100644 Documentation/mainboard/opencellular/elgon2.png (limited to 'Documentation/mainboard/opencellular') diff --git a/Documentation/mainboard/opencellular/elgon.md b/Documentation/mainboard/opencellular/elgon.md new file mode 100644 index 000000000000..37d05e64f5ed --- /dev/null +++ b/Documentation/mainboard/opencellular/elgon.md @@ -0,0 +1,72 @@ +# Elgon + +This page describes how to run coreboot on the [Elgon] compute board +from [OpenCellular]. + +## TODO + +* Add hard reset control + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Model | W25Q128 | ++---------------------+------------+ +| Size | 16 MiB | ++---------------------+------------+ +| In circuit flashing | yes | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | No | ++---------------------+------------+ +| Dual BIOS feature | No | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +### Internal programming + +The SPI flash can be accessed using [flashrom]. + +### External programming + +The EVT board does have a pinheader to flash the SOIC-8 in circuit. +Directly connecting a Pomona test-clip on the flash is also possible. + +TODO: pinout + +**Total board view of EVT** + +![][elgon1] + +[elgon1]: elgon1.png + +**Closeup view of SOIC-8 flash IC, programming pin header and +USB serial connector of EVT** + +![][elgon2] + +[elgon2]: elgon2.png + +## Technology + +```eval_rst ++---------------+----------------------------------------+ +| SoC | :doc:`../../soc/cavium/cn81xx/index` | ++---------------+----------------------------------------+ +| CPU | Cavium ARMv8-Quadcore `CN81XX`_ | ++---------------+----------------------------------------+ + +.. _CN81XX: https://www.cavium.com/product-octeon-tx-cn80xx-81xx.html +``` + +[Elgon]: https://github.com/Telecominfraproject/OpenCellular +[OpenCellular]: https://code.fb.com/connectivity/introducing-opencellular-an-open-source-wireless-access-platform/ +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/opencellular/elgon1.png b/Documentation/mainboard/opencellular/elgon1.png new file mode 100644 index 000000000000..c1eb5441f42d Binary files /dev/null and b/Documentation/mainboard/opencellular/elgon1.png differ diff --git a/Documentation/mainboard/opencellular/elgon2.png b/Documentation/mainboard/opencellular/elgon2.png new file mode 100644 index 000000000000..f12a734919b9 Binary files /dev/null and b/Documentation/mainboard/opencellular/elgon2.png differ -- cgit v1.2.3