From 8120759d90f7e5164a600f21bdd04b8878ba8259 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 28 Aug 2018 20:37:58 +0200 Subject: Documentation/nb/intel/sandybridge/nri_registers.md: Fix mistake According to a comment on fa1a07b, the 100MHz clock is the Ivy Bridge only clock, not the 133MHz one. Change-Id: I28fed4a9264b96f93b9e88325f547a5db512514c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/28377 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- Documentation/northbridge/intel/sandybridge/nri_registers.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/northbridge') diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md index d5857ec6157f..aa16644b1754 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_registers.md +++ b/Documentation/northbridge/intel/sandybridge/nri_registers.md @@ -2137,8 +2137,8 @@ Please handle with care ! +===========+==================================================================+ | 0:7| Selected multiplier: 100Mhz [7,12], 133Mhz [3,19] | +-----------+------------------------------------------------------------------+ -| 8 | - 1: 100Mhz reference clock | -| | - 0: 133Mhz reference clock (Ivy Bridge only) | +| 8 | - 1: 100Mhz reference clock (Ivy Bridge only) | +| | - 0: 133Mhz reference clock | +-----------+------------------------------------------------------------------+ | 31 | PLL busy | +-----------+------------------------------------------------------------------+ -- cgit v1.2.3