From 3b0303dbe8c4883b329cab151de33d952baea02a Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 18 Jun 2022 11:53:47 +0200 Subject: Doc/soc/intel/mp_init: Mark up Reference section title as title MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It’s a section title, so mark it up as a title as it’s done similarily in other documents. Change-Id: If9d524afe6f80ae1b2704d11617786ee923814b2 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/65215 Tested-by: build bot (Jenkins) Reviewed-by: Elyes Haouas --- Documentation/soc/intel/mp_init/mp_init.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/soc/intel/mp_init/mp_init.md') diff --git a/Documentation/soc/intel/mp_init/mp_init.md b/Documentation/soc/intel/mp_init/mp_init.md index 7284e8a1c55e..f7776e511eb7 100644 --- a/Documentation/soc/intel/mp_init/mp_init.md +++ b/Documentation/soc/intel/mp_init/mp_init.md @@ -51,6 +51,6 @@ option in order to perform SGX and C6DRAM enabling. Typically all platforms supported by FSP 2.1 specification will have external PPI service feature implemented. -[References] +## References - [PPI](../fsp/ppi/ppi.md) - [MP Service PPI](../fsp/ppi/mp_service_ppi.md) -- cgit v1.2.3