From ef164196cbe6d703366b61070b6b6f1a6bc0038f Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 3 Nov 2021 10:11:35 +0000 Subject: Documentation: Add some notes about how to integrate FSP While we don't _want_ FSP, we can't get around it sometimes. But when using it, we can still try to establish best practices to make life easier for everybody. Change-Id: I4efd273e4141dc6dc4cf8bdebda9cffd0d7cc1a1 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/58886 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- Documentation/soc/intel/fsp/index.md | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'Documentation/soc/intel') diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md index 912c44beeadb..feeb5e943319 100644 --- a/Documentation/soc/intel/fsp/index.md +++ b/Documentation/soc/intel/fsp/index.md @@ -2,6 +2,18 @@ This section contains documentation about Intel-FSP in public domain. +## Integration Guidelines + +Some guiding principles when working on the glue to integrate FSP into +coreboot, e.g. on how to configure a board in devicetree when that affects +the way FSP works: + +* It should be possible to replace FSP based boot with a native coreboot + implementation for a given chipset without touching the mainboard code. +* The devicetree configures coreboot and part of what coreboot does with the + information is setting some FSP UPDs. The devicetree isn't supposed to + directly configure FSP. + ## Bugs As Intel doesn't even list known bugs, they are collected here until those are fixed. If possible a workaround is described here as well. -- cgit v1.2.3