From 9b7e990d18d5f6212df6ea967428c28b802e1b64 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Wed, 22 May 2019 18:32:46 +0200 Subject: doc/mb/upsquared: Add documentation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds documentation about the UP² mainboard and the IFWI used by Apollolake platform. Change-Id: Ic708ddbd2616eee4e5ec2740b3eac18b408bde38 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/32935 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- Documentation/mainboard/up/squared/bottom.dia | Bin 0 -> 1112 bytes Documentation/mainboard/up/squared/bottom.jpg | Bin 38689 -> 48761 bytes .../up/squared/header_40pin_gpio_uart1.dia | Bin 0 -> 1853 bytes .../up/squared/header_40pin_gpio_uart1.svg | 126 ++++++++++++++++ .../up/squared/header_cn16_10pin_uart0.dia | Bin 0 -> 1752 bytes .../up/squared/header_cn16_10pin_uart0.svg | 112 ++++++++++++++ .../mainboard/up/squared/header_cn22_12pin_spi.dia | Bin 0 -> 2240 bytes .../mainboard/up/squared/header_cn22_12pin_spi.svg | 165 +++++++++++++++++++++ Documentation/mainboard/up/squared/index.md | 102 +++++++++++-- .../soc/intel/apollolake/flash_layout.dia | Bin 0 -> 1988 bytes .../soc/intel/apollolake/flash_layout.svg | 122 +++++++++++++++ Documentation/soc/intel/apollolake/index.md | 17 +++ Documentation/soc/intel/index.md | 1 + 13 files changed, 629 insertions(+), 16 deletions(-) create mode 100644 Documentation/mainboard/up/squared/bottom.dia create mode 100644 Documentation/mainboard/up/squared/header_40pin_gpio_uart1.dia create mode 100644 Documentation/mainboard/up/squared/header_40pin_gpio_uart1.svg create mode 100644 Documentation/mainboard/up/squared/header_cn16_10pin_uart0.dia create mode 100644 Documentation/mainboard/up/squared/header_cn16_10pin_uart0.svg create mode 100644 Documentation/mainboard/up/squared/header_cn22_12pin_spi.dia create mode 100644 Documentation/mainboard/up/squared/header_cn22_12pin_spi.svg create mode 100644 Documentation/soc/intel/apollolake/flash_layout.dia create mode 100644 Documentation/soc/intel/apollolake/flash_layout.svg create mode 100644 Documentation/soc/intel/apollolake/index.md (limited to 'Documentation') diff --git a/Documentation/mainboard/up/squared/bottom.dia b/Documentation/mainboard/up/squared/bottom.dia new file mode 100644 index 000000000000..f298d669ab7f Binary files /dev/null and b/Documentation/mainboard/up/squared/bottom.dia differ diff --git a/Documentation/mainboard/up/squared/bottom.jpg b/Documentation/mainboard/up/squared/bottom.jpg index f9aa85db50a2..3c066a23ad98 100644 Binary files a/Documentation/mainboard/up/squared/bottom.jpg and b/Documentation/mainboard/up/squared/bottom.jpg differ diff --git a/Documentation/mainboard/up/squared/header_40pin_gpio_uart1.dia b/Documentation/mainboard/up/squared/header_40pin_gpio_uart1.dia new file mode 100644 index 000000000000..4efc0183e41d Binary files /dev/null and b/Documentation/mainboard/up/squared/header_40pin_gpio_uart1.dia differ diff --git a/Documentation/mainboard/up/squared/header_40pin_gpio_uart1.svg b/Documentation/mainboard/up/squared/header_40pin_gpio_uart1.svg new file mode 100644 index 000000000000..16f6397de40f --- /dev/null +++ b/Documentation/mainboard/up/squared/header_40pin_gpio_uart1.svg @@ -0,0 +1,126 @@ + + + + + 40 pin GPIO header + + + GND + + + UART1 + TX + + + UART1 + RX + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 + + + 4 + + + 2 + + + 3 + + + 5 + + + 7 + + + 8 + + + 6 + + + 9 + + + 11 + + + 12 + + + 10 + + + + + + + + + + + + + + + + + diff --git a/Documentation/mainboard/up/squared/header_cn16_10pin_uart0.dia b/Documentation/mainboard/up/squared/header_cn16_10pin_uart0.dia new file mode 100644 index 000000000000..a35245b9cc4d Binary files /dev/null and b/Documentation/mainboard/up/squared/header_cn16_10pin_uart0.dia differ diff --git a/Documentation/mainboard/up/squared/header_cn16_10pin_uart0.svg b/Documentation/mainboard/up/squared/header_cn16_10pin_uart0.svg new file mode 100644 index 000000000000..43efc77ac528 --- /dev/null +++ b/Documentation/mainboard/up/squared/header_cn16_10pin_uart0.svg @@ -0,0 +1,112 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 + + + 2 + + + 5 + + + 4 + + + 3 + + + 6 + + + 9 + + + 8 + + + 7 + + + 10 + + + GND + + + UART0 + RX + + + UART0 + TX + + + + + + + + + + + + + + + + + + 10 pin UART0/USB2 header (CN16) + + diff --git a/Documentation/mainboard/up/squared/header_cn22_12pin_spi.dia b/Documentation/mainboard/up/squared/header_cn22_12pin_spi.dia new file mode 100644 index 000000000000..ab556ff819f3 Binary files /dev/null and b/Documentation/mainboard/up/squared/header_cn22_12pin_spi.dia differ diff --git a/Documentation/mainboard/up/squared/header_cn22_12pin_spi.svg b/Documentation/mainboard/up/squared/header_cn22_12pin_spi.svg new file mode 100644 index 000000000000..7853fb7e7c99 --- /dev/null +++ b/Documentation/mainboard/up/squared/header_cn22_12pin_spi.svg @@ -0,0 +1,165 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 9 + + + 5 + + + 7 + + + 8 + + + 1 + + + 4 + + + 3 + + + 2 + + + 6 + + + 11 + + + 12 + + + 10 + + + SPI header (CN22) + + + + + + + + + + + + + GND + + + GND + + + + + + + + MISO + + + + + + + + VCC + 1.8V + + + #HOLD + + + + + + + + + + + + + CLK + + + + + + + + MOSI + + + + + + + + #CS + + diff --git a/Documentation/mainboard/up/squared/index.md b/Documentation/mainboard/up/squared/index.md index dcf3ed192ded..9242f76d8d17 100644 --- a/Documentation/mainboard/up/squared/index.md +++ b/Documentation/mainboard/up/squared/index.md @@ -7,6 +7,12 @@ ### Bottom ![][overview_bottom] +* **Legend** + * [BLUE][header_cn16_link]: UART0 / USB connector + * [GREEN][header_gpio_link]: UART1 / GPIO header + * [RED][header_cn22_link]: SPI header + * YELLOW: Indicates pin 1 + ## Mainboard components ### Platform ```eval_rst @@ -46,6 +52,79 @@ +---------------------+------------+ ``` +### Debugging +#### UART0 (CN16) +This connector is located on the **bottom** side (see [here][overview_bottom_link]). +![][header_cn16] + + +#### UART1 (GPIO header) +The GPIO header is located on the **bottom** side (see [here][overview_bottom_link]). +![][header_gpio] + +## Building and flashing coreboot +### Using the SPI header +The SPI header is located on the **bottom** side (see [here][overview_bottom_link]). +![][header_cn22] + +### Preperations +In order to build coreboot, it's neccessary to extract some files from the vendor firmware. Make sure that you have a fully working dump. +```bash +[upsquared]$ ls +firmware_vendor.rom +``` + +```bash +[upsquared]$ mkdir extracted && cd extracted +[extracted]$ ifdtool -x ../firmware_vendor.rom +File ../firmware_vendor.rom is 16777216 bytes +Peculiar firmware descriptor, assuming Ibex Peak compatibility. + Flash Region 0 (Flash Descriptor): 00000000 - 00000fff + Flash Region 1 (BIOS): 00001000 - 00efefff + Flash Region 2 (Intel ME): 07fff000 - 00000fff (unused) + Flash Region 3 (GbE): 07fff000 - 00000fff (unused) + Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused) + Flash Region 5 (Reserved): 00eff000 - 00ffefff + Flash Region 6 (Reserved): 07fff000 - 00000fff (unused) + Flash Region 7 (Reserved): 07fff000 - 00000fff (unused) + Flash Region 8 (EC): 07fff000 - 00000fff (unused) +``` + +```bash +flashregion_0_flashdescriptor.bin +flashregion_1_bios.bin +flashregion_5_reserved.bin +``` + +### Clean up +```bash +[coreboot]$ make distclean +``` + +### Configuring +```bash +[coreboot]$ touch .config +[coreboot]$ ./util/scripts/config --enable VENDOR_UP +[coreboot]$ ./util/scripts/config --enable BOARD_UP_SQUARED +[coreboot]$ ./util/scripts/config --enable NEED_IFWI +[coreboot]$ ./util/scripts/config --enable HAVE_IFD_BIN +[coreboot]$ ./util/scripts/config --set-str IFWI_FILE_NAME "" +[coreboot]$ ./util/scripts/config --set-str IFD_BIN_PATH "" +[coreboot]$ make olddefconfig +``` + +### Building +```bash +[coreboot]$ make +``` + +Now you should have a working and ready to use coreboot build at `build/coreboot.rom`. + +### Flashing +```bash +[coreboot]$ flashrom -p -w build/coreboot.rom +``` + ## Board status ### Working - bootblock, romstage, ramstage @@ -78,22 +157,13 @@ - mini PCIe - flashing with flashrom internally using Linux -## Building and flashing coreboot -### Building - -```bash -make distclean -touch .config -./util/scripts/config --enable VENDOR_UP -./util/scripts/config --enable BOARD_UP_SQUARED -./util/scripts/config --enable NEED_IFWI -./util/scripts/config --enable HAVE_IFD_BIN -./util/scripts/config --set-str IFWI_FILE_NAME "" -./util/scripts/config --set-str IFD_BIN_PATH "" -make olddefconfig -``` - -### Flashing +[header_cn16]: header_cn16_10pin_uart0.svg +[header_cn16_link]: #uart0-cn16 +[header_cn22]: header_cn22_12pin_spi.svg +[header_cn22_link]: #using-the-spi-header +[header_gpio]: header_40pin_gpio_uart1.svg +[header_gpio_link]: #uart1-gpio-header [overview_top]: top.jpg [overview_bottom]: bottom.jpg +[overview_bottom_link]: #bottom diff --git a/Documentation/soc/intel/apollolake/flash_layout.dia b/Documentation/soc/intel/apollolake/flash_layout.dia new file mode 100644 index 000000000000..4ea544061906 Binary files /dev/null and b/Documentation/soc/intel/apollolake/flash_layout.dia differ diff --git a/Documentation/soc/intel/apollolake/flash_layout.svg b/Documentation/soc/intel/apollolake/flash_layout.svg new file mode 100644 index 000000000000..9322875d90f5 --- /dev/null +++ b/Documentation/soc/intel/apollolake/flash_layout.svg @@ -0,0 +1,122 @@ + + + + + + + + + DEVICE_EXTENSION + + + + + + + BIOS + + + + + + + IFD + + + + + + + IFWI + + + + + + + + + + + + + + + + + + + + + FMAP + + + + + + + CONSOLE + + + + + + + COREBOOT(CBFS) + + + + + + + BIOS_UNUSABLE + + + + + + + MRC + + + + + + + OBB + + + + + + + + + + + + + + + + + TXE + + + + + + + BOOTBLOCK + + + + + + + + + + + + diff --git a/Documentation/soc/intel/apollolake/index.md b/Documentation/soc/intel/apollolake/index.md new file mode 100644 index 000000000000..d4a5ee51ae76 --- /dev/null +++ b/Documentation/soc/intel/apollolake/index.md @@ -0,0 +1,17 @@ +# Apollolake +## SPI flash layout + +![][apl_flash_layout] + +With Apollolake Intel invented another flash layout for x86 firmware called IFWI (Intel FirmWare Image). + +Usually on x86 platforms the bootblock is stored at the end of the bios region +and the Intel ME / TXE has its own IFD region. On Apollolake both have been +moved into the IFWI region, which is a subregion of "BIOS", since it allows to +store multiple firmware components. + +The IFWI region can be manipulated by `ifwitool`. + +[apl_flash_layout]: flash_layout.svg + + diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md index 86f4de715599..f30ff9a1d607 100644 --- a/Documentation/soc/intel/index.md +++ b/Documentation/soc/intel/index.md @@ -9,3 +9,4 @@ This section contains documentation about coreboot on specific Intel SOCs. - [Ice Lake/9th Gen Core-i series](icelake/index.md) - [MP Initialization](mp_init/mp_init.md) - [Firmware Interface Table](fit.md) +- [Apollolake](apollolake/index.md) -- cgit v1.2.3