From bbe876250f2bc5045cc3947c024e6f70330cc9ba Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 28 May 2022 12:32:02 -0600 Subject: Documentation: Fix a few spelling issues Signed-off-by: Martin Roth Change-Id: I47add663f3021170b840203ce229acf836b7a1c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64749 Tested-by: build bot (Jenkins) Reviewed-by: Elyes Haouas Reviewed-by: Felix Singer --- Documentation/getting_started/architecture.md | 2 +- Documentation/mainboard/acer/g43t-am3.md | 2 +- Documentation/northbridge/intel/sandybridge/nri_registers.md | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/getting_started/architecture.md b/Documentation/getting_started/architecture.md index 09fb96031fd9..8910d775f794 100644 --- a/Documentation/getting_started/architecture.md +++ b/Documentation/getting_started/architecture.md @@ -3,7 +3,7 @@ ## Overview ![][architecture] -[architecture]: comparision_coreboot_uefi.svg +[architecture]: comparison_coreboot_uefi.svg ## Stages coreboot consists of multiple stages that are compiled as separate binaries and diff --git a/Documentation/mainboard/acer/g43t-am3.md b/Documentation/mainboard/acer/g43t-am3.md index e57009c4debd..07d23c6dea85 100644 --- a/Documentation/mainboard/acer/g43t-am3.md +++ b/Documentation/mainboard/acer/g43t-am3.md @@ -134,7 +134,7 @@ SPI_ROM1 header while the board is off and disconnected from power. There seems to be a diode that prevents the external programmer from powering the whole board. -The signal assigment on the header is identical to the pinout of the flash +The signal assignment on the header is identical to the pinout of the flash chip. The pinout diagram below is valid when the PCI slots are on the left and the CPU is on the right. Note that HOLD# and WP# must be pulled high (to VCC) to be able to flash the chip. diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md index 32bd3d1e2867..6abf5c9eaa93 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_registers.md +++ b/Documentation/northbridge/intel/sandybridge/nri_registers.md @@ -1899,7 +1899,7 @@ Please handle with care! +===========+==================================================================+ | 0:7| PDWN_idle_counter, This defines the rank indle period in DCLK | | | cycles that causes power-down entrance. The minimum value | -| | should be greater then or equal to the worst roundtrip time | +| | should be greater than or equal to the worst roundtrip time | | | plus burst length. | +-----------+------------------------------------------------------------------+ | 8:10| PDWN_mode, selects the mode of power-down: | -- cgit v1.2.3