From e0e784a456c4d64e5e88ce578371fe6c538db559 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Wed, 26 Nov 2014 19:25:47 +0000 Subject: Add UCB RISCV support for architecture, soc, and emulation mainboard.. Works in the RISCV version of QEMU. Note that the lzmadecode is so unclean that it needs a lot of work. A cleanup is in progress. We decided in Prague to do this as one thing, because it forms a nice case study of the bare minimum you need to add to get a new architecture going in qemu. Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d Signed-off-by: Ronald G. Minnich Reviewed-on: http://review.coreboot.org/7584 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/arch/riscv/misc.c | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 src/arch/riscv/misc.c (limited to 'src/arch/riscv/misc.c') diff --git a/src/arch/riscv/misc.c b/src/arch/riscv/misc.c new file mode 100644 index 000000000000..6e64028777dd --- /dev/null +++ b/src/arch/riscv/misc.c @@ -0,0 +1,9 @@ +#include + +void init_timer(void) +{ +} + +void udelay(unsigned int n) +{ +} -- cgit v1.2.3