From a5b265bb0ca85cec02c92046904dc0f44f7d6639 Mon Sep 17 00:00:00 2001 From: Xiang Wang Date: Wed, 29 Aug 2018 14:59:32 +0800 Subject: riscv: separately define stack locations at different stages BOOTBLOCK/ROMSTAGE run in CAR/scratchpad. When RAMSTAGE begins execution will enable cache, then CAR will disappear. So the Stack will be separated. Change-Id: I37a0c1928052cabf61ba5c25b440363b75726782 Signed-off-by: Xiang Wang Reviewed-on: https://review.coreboot.org/28383 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/arch/riscv/include/arch/memlayout.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/arch/riscv') diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h index 9097cf572161..7baab7647931 100644 --- a/src/arch/riscv/include/arch/memlayout.h +++ b/src/arch/riscv/include/arch/memlayout.h @@ -20,6 +20,20 @@ #define STACK(addr, size) REGION(stack, addr, size, 4096) +#if defined(__PRE_RAM__) + #define CAR_STACK(addr, size) \ + REGION(car_stack, addr, size, 4K) \ + ALIAS_REGION(car_stack, stack) + #define MEM_STACK(addr, size) \ + REGION(mem_stack, addr, size, 4K) +#else + #define CAR_STACK(addr, size) \ + REGION(car_stack, addr, size, 4K) + #define MEM_STACK(addr, size) \ + REGION(mem_stack, addr, size, 4K) \ + ALIAS_REGION(mem_stack, stack) +#endif + /* TODO: Need to add DMA_COHERENT region like on ARM? */ #endif /* __ARCH_MEMLAYOUT_H */ -- cgit v1.2.3