From bd06a297d5c1a0d75056e505a4f35568708e190e Mon Sep 17 00:00:00 2001 From: Maximilian Brune Date: Thu, 9 Nov 2023 17:53:34 +0100 Subject: arch/riscv/ramstage.S: Add comments for passed arguments Signed-off-by: Maximilian Brune Change-Id: Ib1af1359249008d9eba351271637748a7edcec26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78966 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/arch/riscv/ramstage.S | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/arch/riscv') diff --git a/src/arch/riscv/ramstage.S b/src/arch/riscv/ramstage.S index 921c46d8a579..954b1555b3e6 100644 --- a/src/arch/riscv/ramstage.S +++ b/src/arch/riscv/ramstage.S @@ -7,7 +7,11 @@ .section ".text._start", "ax", %progbits .globl _start _start: - /* cbmem_top is passed via a2 */ + # The romstage may pass the following arguments: + # a0: the value of mhartid + # a1: a pointer to the flattened devicetree + # a2: cbmem_top + la t0, _cbmem_top_ptr #if __riscv_xlen == 32 sw a2, (t0) @@ -28,6 +32,7 @@ _start: # initialize hart-local storage csrr a0, mhartid + #NOTE a1 contains FDT and should not be cluttered above call hls_init li a0, CONFIG_RISCV_WORKING_HARTID -- cgit v1.2.3