From 32c8de10b03d0f7fccd4e4dc10a20f97e57cc428 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 2 Nov 2019 09:39:36 +0200 Subject: Rangeley: Fix incorrect BCLK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not all Rangeley SKUs have a fixed 100MHz BCLK. As per BIOS Writer's Guide, BCLK is available in MSR_FSB_FREQ 0xCD[1:0]. Using fixed BCLK was causing wrong values of core frequencies in _PSS table for SKUs that do not have BCLK=100MHz. Change-Id: Id8e0244fab0283b74870950cb00a95aab2a7201f Signed-off-by: Hannah Williams Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35348 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/cpu/intel/common/fsb.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/cpu/intel/common/fsb.c') diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 14dbd60e2402..0004eade891c 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -32,6 +32,7 @@ static int get_fsb_tsc(int *fsb, int *ratio) static const short core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 }; static const short core2_fsb[8] = { 266, 133, 200, 166, 333, 100, 400, -1 }; static const short f2x_fsb[8] = { 100, 133, 200, 166, 333, -1, -1, -1 }; + static const short rangeley_fsb[4] = { 83, 100, 133, 116 }; msr_t msr; get_fms(&c, cpuid_eax(1)); @@ -56,10 +57,13 @@ static int get_fsb_tsc(int *fsb, int *ratio) case 0x3a: /* IvyBridge BCLK fixed at 100MHz */ case 0x3c: /* Haswell BCLK fixed at 100MHz */ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ - case 0x4d: /* Rangeley BCLK fixed at 100MHz */ *fsb = 100; *ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff; break; + case 0x4d: /* Rangeley */ + *fsb = rangeley_fsb[rdmsr(MSR_FSB_FREQ).lo & 3]; + *ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff; + break; default: return -2; } -- cgit v1.2.3