From f2cae5085c49904b827d867dbf8d1a8b0d284c74 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Fri, 25 Oct 2019 15:13:04 -0600 Subject: cpu/intel/car: Add EC software sync to Intel romstage Perform EC software sync in romstage, before memory training is started. Because the ChromeOS EC will not currently perform USB-PD negotiation until it jumps to running its RW code, this allows the system to get access to more power earlier in the boot flow. This is guarded by CONFIG_VBOOT_EARLY_EC_SYNC. BUG=b:112198832 BRANCH=none TEST=EC software sync works in update and non-update case. No significant effect on boot time (~6 ms). Change-Id: I31f3407a2afcbf288461fab1397f965f025bc07c Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/36211 Reviewed-by: Aaron Durbin Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/cpu/intel/car/romstage.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/cpu') diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 1525233e390c..9d196356e373 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -21,6 +21,7 @@ #include #include #include +#include /* If we do not have a constrained _car_stack region size, use the following as a guideline for acceptable stack usage. */ @@ -51,6 +52,9 @@ static void romstage_main(unsigned long bist) for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard; + if (CONFIG(VBOOT_EARLY_EC_SYNC)) + vboot_sync_ec(); + mainboard_romstage_entry(); /* Check the stack. */ -- cgit v1.2.3