From bb41aba0d8c3c3cbfee44b0f7267e78fb7d012ee Mon Sep 17 00:00:00 2001 From: Keith Short Date: Thu, 16 May 2019 14:07:43 -0600 Subject: post_code: add post code for invalid vendor binary Add a new post code POST_INVALID_VENDOR_BINARY, used when coreboot fails to locate or validate a vendor supplied binary. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4 Signed-off-by: Keith Short Reviewed-on: https://review.coreboot.org/c/coreboot/+/32772 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/drivers/intel/fsp1_1/raminit.c | 14 ++++++++------ src/drivers/intel/fsp2_0/memory_init.c | 6 ++++-- src/drivers/intel/fsp2_0/silicon_init.c | 3 ++- 3 files changed, 14 insertions(+), 9 deletions(-) (limited to 'src/drivers') diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 726cc26a0c39..fc6f8480892e 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -195,9 +195,6 @@ void raminit(struct romstage_params *params) } #if CONFIG(DISPLAY_HOBS) - if (hob_list_ptr == NULL) - die("ERROR - HOB pointer is NULL!\n"); - /* * Verify that FSP is generating the required HOBs: * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0 @@ -244,7 +241,10 @@ void raminit(struct romstage_params *params) "ERROR - Missing one or more required FSP HOBs!\n"); /* Display the HOBs */ - print_hob_type_structure(0, hob_list_ptr); + if (hob_list_ptr != NULL) + print_hob_type_structure(0, hob_list_ptr); + else + printk(BIOS_ERR, "ERROR - HOB pointer is NULL!\n"); #endif /* Get the address of the CBMEM region for the FSP reserved memory */ @@ -274,14 +274,16 @@ void raminit(struct romstage_params *params) printk(BIOS_DEBUG, "0x%08x: Chipset reserved bytes reported by FSP\n", (unsigned int)delta_bytes); - die("Please verify the chipset reserved size\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "Please verify the chipset reserved size\n"); } #endif } /* Verify the FSP 1.1 HOB interface */ if (fsp_verification_failure) - die("ERROR - coreboot's requirements not met by FSP binary!\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "ERROR - coreboot's requirements not met by FSP binary!\n"); /* Display the memory configuration */ report_memory_config(); diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index b3afb98c4d23..449b57d03ebb 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -277,7 +277,8 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base); if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) - die("Invalid FSPM signature!\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "Invalid FSPM signature!\n"); /* Copy the default values from the UPD area */ memcpy(&fspm_upd, upd, sizeof(fspm_upd)); @@ -290,7 +291,8 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, /* Fill common settings on behalf of chipset. */ if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version, memmap) != CB_SUCCESS) - die("FSPM_ARCH_UPD not found!\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "FSPM_ARCH_UPD not found!\n"); /* Give SoC and mainboard a chance to update the UPD */ platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version); diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 402b05d55e04..b0a697d8cbc3 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -33,7 +33,8 @@ static void do_silicon_init(struct fsp_header *hdr) supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE) - die("Invalid FSPS signature\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "Invalid FSPS signature\n"); upd = xmalloc(sizeof(FSPS_UPD)); -- cgit v1.2.3