From 2437fe9dfab8e4056b633a39d51d07aa81ab3c9d Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 4 Oct 2019 13:59:29 +0200 Subject: sb/intel/i82801gx: Move CIR init to a common place Some boards with the G41 chipset lacked programming CIR, so this change add that to those boards too. Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/35795 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/asus/p5qpl-am/romstage.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'src/mainboard/asus/p5qpl-am/romstage.c') diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index dc589a591892..30480ad3d5d6 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -131,7 +131,6 @@ static int setup_sio_gpio(void) static void mb_lpc_setup(void) { - u32 reg32; /* Set the value for GPIO base address register and enable GPIO. */ pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); @@ -142,10 +141,7 @@ static void mb_lpc_setup(void) RCBA8(0x31ff) = 0x03; RCBA8(0x31ff); - reg32 = RCBA32(GCS); - reg32 |= (1 << 5); - RCBA32(GCS) = reg32; - RCBA32(CG) = 0x00000001; + ich7_setup_cir(); } static void ich7_enable_lpc(void) -- cgit v1.2.3