From af4bd5633debc8838b563c3fadd96e2b4b060ab5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 28 Dec 2021 13:05:56 +0100 Subject: sb/intel: Use `bool` for PCIe coalescing option Retype the `pcie_port_coalesce` devicetree options and related variables to better reflect their bivalue (boolean) nature. Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416 Reviewed-by: Felix Held Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- src/mainboard/google/beltino/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google/beltino') diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 8c54f6a6d093..8eada2532609 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -44,7 +44,7 @@ chip northbridge/intel/haswell register "pcie_port_force_aspm" = "0x10" # Enable port coalescing - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP register "icc_clock_disable" = "0x01220000" -- cgit v1.2.3