From 6cfe2624a24eb07279cda6356b0195539e1d67d3 Mon Sep 17 00:00:00 2001 From: Tony Huang Date: Thu, 7 Jul 2022 17:57:55 +0800 Subject: mb/google/brya/var/agah: Disable thunderbolt interface Agah doesn't support TBT interface so disable it in devicetree, for fitimage configuration is at chrome-internal:4846869. BUG=b:224423318 TEST=Build and check DUT boots. Change-Id: I1eb43e86de5debf24ebde6eace14fe04bad5e5b1 Signed-off-by: Tony Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/65699 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/brya/variants/agah/overridetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/mainboard/google/brya/variants/agah/overridetree.cb') diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb index 007b188ff090..550dab60fbd8 100644 --- a/src/mainboard/google/brya/variants/agah/overridetree.cb +++ b/src/mainboard/google/brya/variants/agah/overridetree.cb @@ -59,6 +59,12 @@ chip soc/intel/alderlake }" device domain 0 on + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_pcie_rp2 off end + + device ref tcss_dma0 off end + device ref tcss_dma1 off end device ref pcie4_0 on # Enable CPU PCIe RP 1 using CLKREQ 0 and CLKSRC 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ -- cgit v1.2.3