From ec877d633d0db3b40c28d2ef198313ab688cd3d4 Mon Sep 17 00:00:00 2001 From: Tracy Wu Date: Thu, 13 Jan 2022 21:53:02 +0800 Subject: mb/google/brya/variants/*: Add cpu pcie rp flags Along with commit f94405219c (soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs), we need to set cpu pcie rp flags in devicetree now. This CL is to add proper cpu pcie flags (PCIE_RP_LTR and PCIE_RP_AER) in all intel projects or system will be blocked at PKGC2R with root port LTR not enable. BUG=b:214009181 TEST=Build and DUT (Kano) can enter deeper PKGC state normally. Signed-off-by: Tracy Wu Change-Id: I0d8721bf1454448b7fc14655f0e4513001469a18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61073 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/brask/overridetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/google/brya/variants/brask/overridetree.cb') diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index d60183bcb728..b9c8edbe4f97 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -97,6 +97,7 @@ chip soc/intel/alderlake register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 0, .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end device ref tcss_dma0 on -- cgit v1.2.3