From 03c3d5d68ea5c4758c0e3dc9dd15a7013b2105bd Mon Sep 17 00:00:00 2001 From: Mark Hsieh Date: Wed, 10 Nov 2021 20:58:49 +0800 Subject: mb/google/brya/var/gimble: Improve USB2 eye diagram of DB Type-C port - Set MAX OC1 to USB2_C1 BUG=b:205676803 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh Change-Id: Idcf13ad072ae5d7a897f54adb19e6b2b068609dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59100 Tested-by: build bot (Jenkins) Reviewed-by: Zhuohao Lee --- src/mainboard/google/brya/variants/gimble/overridetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/google/brya/variants/gimble') diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index c015009c0077..842dd00c0665 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -34,6 +34,7 @@ chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" register "TcssAuxOri" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # set MAX to USB2_C1 for eye diagram register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # M.2 WWAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port -- cgit v1.2.3