From 3d80d14cd4ed82e74057cea884dcb9bb7588c076 Mon Sep 17 00:00:00 2001
From: Nico Huber <nico.h@gmx.de>
Date: Fri, 12 Jan 2024 16:22:19 +0100
Subject: soc/intel/jasperlake: Drop redundant PcieRpEnable

The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.

Thanks to Nicholas for doing all the mainboard legwork!

Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/dedede/variants/baseboard/ramstage.c | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/mainboard/google/dedede/variants/baseboard/ramstage.c')

diff --git a/src/mainboard/google/dedede/variants/baseboard/ramstage.c b/src/mainboard/google/dedede/variants/baseboard/ramstage.c
index e14e95650d77..d43d08f8561c 100644
--- a/src/mainboard/google/dedede/variants/baseboard/ramstage.c
+++ b/src/mainboard/google/dedede/variants/baseboard/ramstage.c
@@ -6,6 +6,7 @@
 #include <drivers/usb/acpi/chip.h>
 #include <fw_config.h>
 #include <gpio.h>
+#include <soc/pci_devs.h>
 #include <ec/google/chromeec/ec.h>
 #include <device/pci_ops.h>
 #include <intelblocks/power_limit.h>
-- 
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