From 6d92ab8932ee098516af3e0d208fad536f5c1c55 Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Fri, 24 Jul 2020 09:16:05 +0530 Subject: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur This patch updates the SLP_Sx assertion width and power cycle duration for the dedede platforms. Power cycle duration: With default value, S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0 With value set to 1, S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0 BUG=b:159104150 TEST=Verified that the power cycle duration is ~1.2s with global reset on waddledoo. Change-Id: I7079cbd564288b5d5b69e07661434439365063d3 Signed-off-by: V Sowmya Reviewed-on: https://review.coreboot.org/c/coreboot/+/43792 Tested-by: build bot (Jenkins) Reviewed-by: Aamir Bohra Reviewed-by: Sridhar Siricilla Reviewed-by: Maulik V Vaghela Reviewed-by: Ronak Kanabar Reviewed-by: Subrata Banik --- .../google/dedede/variants/baseboard/devicetree.cb | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/mainboard/google/dedede/variants/baseboard') diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index d0609ef0cda2..e7c56568330a 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -166,6 +166,20 @@ chip soc/intel/jasperlake # Skip the CPU repalcement check register "SkipCpuReplacementCheck" = "1" + # Set the minimum assertion width + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "3" # 1s + register "PchPmSlpAMinAssert" = "3" # 98ms + + # NOTE: Duration programmed in the below register should never be smaller than the + # stretch duration programmed in the following registers - + # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + # - PM_CFG.SLP_LAN_MIN_ASST_WDTH + register "PchPmPwrCycDur" = "1" # 1s + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device -- cgit v1.2.3