From 3a1a037231ddb5cdc03d0e147c2335de0f1c8ad6 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Mon, 9 Mar 2020 18:20:07 -0700
Subject: mb/google/deltaur: add deltaur mainboard initial support

Created a new Google baseboard using Tiger Lake named deltaur, taking
volteer as a starting point.

BUG=b:151102807
TEST=make build successful

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib98f328df22f39e7d9d625a3292954881ee15b15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
---
 src/mainboard/google/deltaur/dsdt.asl | 51 +++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)
 create mode 100644 src/mainboard/google/deltaur/dsdt.asl

(limited to 'src/mainboard/google/deltaur/dsdt.asl')

diff --git a/src/mainboard/google/deltaur/dsdt.asl b/src/mainboard/google/deltaur/dsdt.asl
new file mode 100644
index 000000000000..b6bc8e4248b0
--- /dev/null
+++ b/src/mainboard/google/deltaur/dsdt.asl
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <arch/acpi.h>
+#include "variant/ec.h"
+#include "variant/gpio.h"
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		/* DSDT revision: ACPI v2.0 and up */
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	/* OEM revision */
+)
+{
+	#include <soc/intel/tigerlake/acpi/platform.asl>
+
+	/* global NVS and variables */
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+			#include <soc/intel/tigerlake/acpi/southbridge.asl>
+		}
+	}
+
+	/* Chrome OS specific */
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+	/* VPD support */
+	#include <vendorcode/google/chromeos/acpi/vpd.asl>
+
+	/* Chrome OS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <ec/google/wilco/acpi/superio.asl>
+		/* ACPI code for EC functions */
+		#include <ec/google/wilco/acpi/ec.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}
-- 
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