From e539c8538666d949c01d7bcbd8c714cee5d0148e Mon Sep 17 00:00:00 2001 From: Richard Spiegel Date: Mon, 25 Dec 2017 18:25:58 -0700 Subject: soc/amd/stoneyridge/southbridge.c: Create a GPIO programming function Create a GPIO programming function that can be called from multiple stages (bootblock, romstage and ramstage) that will program only the GPIO specific to the particular stage. Add dummy table to kahlee, grunt and gardenia to be able to test a build. BUG=b:64140392 TEST=Build kahlee, grunt and gardenia with GPIO programming call at bootblock. This call is removed before commit, so bootblock.c is not committed. Change-Id: I88d65c78a186bed9739bc208d5711a31aa3c3bb6 Signed-off-by: Richard Spiegel Reviewed-on: https://review.coreboot.org/22986 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- .../google/kahlee/variants/baseboard/gpio.c | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'src/mainboard/google/kahlee/variants/baseboard/gpio.c') diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 58d947321825..0566320e8084 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -20,6 +20,26 @@ #include #include +/* + * These settings were generated by a spreadsheet. If they need to be updated, + * update the spreadsheet shared with the Grunt development team. + * + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { + + /* GPIO_0 - EC_PCH_PWR_BTN_ODL */ + { GPIO_0, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, +}; + +const static struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { + + /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */ + { GPIO_2, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, +}; + /* * These settings were generated by a spreadsheet. If they need to be updated, * update the spreadsheet shared with the Grunt development team. @@ -260,6 +280,17 @@ const __attribute__((weak)) GPIO_CONTROL *get_gpio_table(void) return agesa_board_gpios; } +const __attribute__((weak)) const struct soc_amd_stoneyridge_gpio + *board_get_gpio(size_t *size) +{ + if (GPIO_TABLE_BOOTBLOCK) { + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; + } + *size = ARRAY_SIZE(gpio_set_stage_ram); + return gpio_set_stage_ram; +} + /* * GPE setup table must match ACPI GPE ASL * { gevent, gpe, direction, level } -- cgit v1.2.3