From 7557c25f10d4cc4f01dcff43b8c4d12e7cd04a5c Mon Sep 17 00:00:00 2001
From: Sunway <lisunwei@huaqin.corp-partner.google.com>
Date: Mon, 10 May 2021 14:49:18 +0800
Subject: mb/google/kukui: Add discrete EMCP LPDDR4X table for Kakadu/Katsu

Add EMCP LPDDR4X DDR FEPRF6432-58A1930 for ram id 9.

BUG=b:186141919
BRANCH=kukui
TEST=New Emcp can boot normally on kakadu/katsu

Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: Ieaf05a0a7b0c0671c07b0df29319ebd91fe63e57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54009
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/kukui/sdram_params/Makefile.inc         |  1 +
 .../sdram-lpddr4x-FEPRF6432-58A1930-4GB.c          | 28 ++++++++++++++++++++++
 2 files changed, 29 insertions(+)
 create mode 100644 src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-FEPRF6432-58A1930-4GB.c

(limited to 'src/mainboard/google/kukui/sdram_params')

diff --git a/src/mainboard/google/kukui/sdram_params/Makefile.inc b/src/mainboard/google/kukui/sdram_params/Makefile.inc
index 4117bf26aeda..cb8f427413c7 100644
--- a/src/mainboard/google/kukui/sdram_params/Makefile.inc
+++ b/src/mainboard/google/kukui/sdram_params/Makefile.inc
@@ -14,6 +14,7 @@ sdram-params += sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB
 sdram-params += sdram-lpddr4x-MT53E1G32D2NP-046-4GB
 sdram-params += sdram-lpddr4x-MT29VZZZCD9GQKPR-046-8GB
 sdram-params += sdram-lpddr4x-MT29VZZZAD9GQFSM-046-4GB
+sdram-params += sdram-lpddr4x-FEPRF6432-58A1930-4GB
 
 $(foreach params,$(sdram-params), \
 	$(eval cbfs-files-y += $(params)) \
diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-FEPRF6432-58A1930-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-FEPRF6432-58A1930-4GB.c
new file mode 100644
index 000000000000..86c3e8f04e9f
--- /dev/null
+++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-FEPRF6432-58A1930-4GB.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/dramc_param.h>
+
+struct sdram_params params = {
+	.source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG,
+	.frequency = 1600,
+	.rank_num = 1,
+	.ddr_geometry = DDR_TYPE_2CH_1RK_4GB_4,
+	.wr_level = {
+		[CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} },
+		[CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} }
+	},
+	.cbt_cs_dly = {
+		[CHANNEL_A] = {0x5, 0x4},
+		[CHANNEL_B] = {0x8, 0x8}
+	},
+	.cbt_final_vref = {
+		[CHANNEL_A] = {0x56, 0x56},
+		[CHANNEL_B] = {0x56, 0x56}
+	},
+	.emi_cona_val = 0xF053F154,
+	.emi_conh_val = 0x44440003,
+	.emi_conf_val = 0x00421000,
+	.chn_emi_cona_val = {0x0444F051, 0x0444F051},
+	.cbt_mode_extern = CBT_NORMAL_MODE,
+	.delay_cell_unit = 868,
+};
-- 
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