From c077b2274b661fb57ffed66b105ece88e30c73b2 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 1 Aug 2019 10:50:35 +0530 Subject: soc/intel/skylake: Make use of common thermal code for SKL This patch ensures skylake soc is using common thermal code from intel common block. TEST=Build and boot soraka Change-Id: I0812daa3536051918ccac973fde8d7f4f949609d Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/34648 Reviewed-by: Furquan Shaikh Reviewed-by: Aamir Bohra Tested-by: build bot (Jenkins) --- src/mainboard/google/poppy/variants/rammus/devicetree.cb | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src/mainboard/google/poppy/variants/rammus') diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 1f73a5903e03..70a4667e9e05 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -172,6 +172,7 @@ chip soc/intel/skylake #| I2C0 | Touchscreen | #| I2C1 | Trackpad | #| I2C5 | Audio | + #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -207,6 +208,7 @@ chip soc/intel/skylake .speed_mhz = 1, .early_init = 1, }, + .pch_thermal_trip = 75, }" # Touchscreen @@ -242,9 +244,6 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_E15" - # PCH Trip Temperature in degree C - register "pch_trip_temp" = "75" - device cpu_cluster 0 on device lapic 0 on end end -- cgit v1.2.3