From 50aa3d99215b558f959fceed891ed04db648739e Mon Sep 17 00:00:00 2001 From: Chris Wang Date: Mon, 20 Feb 2023 10:27:50 +0800 Subject: soc/amd/mendocino: Remove the SPL DPTC parameter The SPL parameter for DPTC settings is not available for STT-enabled platforms. It needs to be removed to avoid confusing STT calculations. BUG=b:265267957 BRANCH=none TEST=Run the WebGL aquarium with 5000 fish and verify that there are no power drop peaks. Change-Id: I8e6dad7d24883f8aadce83ebac401ecd4137d61a Signed-off-by: Chris Wang Reviewed-on: https://review.coreboot.org/c/coreboot/+/73124 Tested-by: build bot (Jenkins) Reviewed-by: Tim Van Patten --- src/mainboard/google/skyrim/variants/baseboard/devicetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/google/skyrim/variants/baseboard') diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index 698d8c3258a6..c92131c2c345 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -260,6 +260,7 @@ chip soc/amd/mendocino register "fast_ppt_limit_mW" = "30000" register "slow_ppt_time_constant_s" = "5" register "stapm_time_constant_s" = "275" + # Remove the sustained_power_limit_mW when STT is enabled register "sustained_power_limit_mW" = "15000" register "thermctl_limit_degreeC" = "100" register "vrm_current_limit_mA" = "28000" -- cgit v1.2.3