From 50863daef8ed75c0cb3dfd375e7622c898de5821 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 1 Oct 2021 14:37:30 -0600 Subject: src/mainboard to src/security: Fix spelling errors These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Angel Pons --- src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb') diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 947672373507..68eb6ea5887e 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -21,7 +21,7 @@ chip soc/amd/picasso }" # Start : OPN Performance Configuration - # (Configuratin that is common for all variants) + # (Configuration that is common for all variants) # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time @@ -232,7 +232,7 @@ chip soc/amd/picasso register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD -- cgit v1.2.3