From 94be1f7399629de0578c56625ddd327cc1123fe4 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Thu, 3 Sep 2020 15:46:56 -0600 Subject: mb/google/zork: Set eMMC presets They should be tuned per board to get the best signal and boot time. This fixes the HS400 preset, so it's correctly set to A. It also changes the SDR50 and DDR50 presets to B. We can't boot correctly when DDR50 is set to A. I chose 1 as the init kHz value since that's what depthcharge uses to calculate the init clock. BUG=b:159823235 TEST=Boot Ezkinil and dump SDHCI preset registers. Signed-off-by: Raul E Rangel Change-Id: Ie2f3497b65d771820ab1a803fec73265547f8906 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45098 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- .../google/zork/variants/baseboard/devicetree_dalboz.cb | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb') diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 40042436d3b2..ae712ee2bee4 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -42,6 +42,16 @@ chip soc/amd/picasso register "emmc_config" = "{ .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + /* + * The reference design was missing a pull-up on the CMD line. + * This means we can't run at the full 400 kHz. By setting this + * to 1 we run at the slowest frequency possible by the + * controller (~97 kHz). + * + * Boards that have the pull-up should correctly set this. + */ + .init_khz_preset = 1, }" register "xhci0_force_gen1" = "0" -- cgit v1.2.3